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comparator in the 1st stage of a 14bit pipeline adc

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urian

urian

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our project is to design a 14bit 80M pipeline adc.The first stage is 4bit(1 bit redundancy) followed by 8 stages of 1.5bit/stage.the decision level of 1.5bit/stage is ±Vref/4,which can tolerated ±Vref/4(or ±Vref/2) offset.I dont know how people think up this method.
and i dont know what are the first stage decision levels either.
Could someone explain it to me please?
thx
 

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