AMSA84
Advanced Member level 2
- Joined
- Aug 24, 2010
- Messages
- 577
- Helped
- 8
- Reputation
- 16
- Reaction score
- 8
- Trophy points
- 1,298
- Location
- Iberian Peninsula
- Activity points
- 6,178
Hi guys.
I have not much experience designing comparators, so I need your help.
From the research I did, there are basically two types of comparators, those which use clock (latch type) and those who not, for example the basic 3-stage comparator (pre-amp, positive feedback, ouput drive) or the comparator with internal feedback (cross coupled bistable) and yet another variant known as Clamped CMOS voltage comparator (Allen's book).
Because I am not interested on using a clock, those last three are of my interest.
From what I read, I concluded that maybe the best one is the comparator with internal feedback (cross coupled bistable) whose circuit is this one:
Is fast, has less delay, relatively good gain;
Regarding this, I would like to hear from you, in your opinion which one is best.
The next question is: What consideration I must have in mind when designing the comparator? Should I use the lowest L in all transistors? The differential pair must have a large W? What current should I point? (I don't have restrictions) All the transistors must be in deep saturation or close to subthreshold? (100mV to 200mV(?)) The tech that I am using is UMC 130nm.
To finish, I tried to design that comparator with internal feedback (cross coupled bistable) based on some examples and some troubles arose. The input reference voltage will vary from 0.7V to 1.8V. In this design, I got this:
It is a strange behavior and I don't know if it might have something to do with the delay. In the first intersection (reference and sawtooth) he doesn't have time to go to zero because 100ps or so the sawtooth is going down and intersects again the reference.
How can I solve this problem? I tried to optimize the comparator to this value but when the reference goes to 0.7V he doesn't work well.
I would like to hear from you and I appreciate any tip.
Thank you very much in advance.
Best regards.
I have not much experience designing comparators, so I need your help.
From the research I did, there are basically two types of comparators, those which use clock (latch type) and those who not, for example the basic 3-stage comparator (pre-amp, positive feedback, ouput drive) or the comparator with internal feedback (cross coupled bistable) and yet another variant known as Clamped CMOS voltage comparator (Allen's book).
Because I am not interested on using a clock, those last three are of my interest.
From what I read, I concluded that maybe the best one is the comparator with internal feedback (cross coupled bistable) whose circuit is this one:
Is fast, has less delay, relatively good gain;
Regarding this, I would like to hear from you, in your opinion which one is best.
The next question is: What consideration I must have in mind when designing the comparator? Should I use the lowest L in all transistors? The differential pair must have a large W? What current should I point? (I don't have restrictions) All the transistors must be in deep saturation or close to subthreshold? (100mV to 200mV(?)) The tech that I am using is UMC 130nm.
To finish, I tried to design that comparator with internal feedback (cross coupled bistable) based on some examples and some troubles arose. The input reference voltage will vary from 0.7V to 1.8V. In this design, I got this:
It is a strange behavior and I don't know if it might have something to do with the delay. In the first intersection (reference and sawtooth) he doesn't have time to go to zero because 100ps or so the sawtooth is going down and intersects again the reference.
How can I solve this problem? I tried to optimize the comparator to this value but when the reference goes to 0.7V he doesn't work well.
I would like to hear from you and I appreciate any tip.
Thank you very much in advance.
Best regards.
Last edited by a moderator: