aswin_98
Newbie
Forgive me if this is poorly formatted, this is my first post.
As you can see I am comparing the voltages across two resistors that are clamped up using some MOSFETs. Please ignore the bottom MOSFETs (gate connected to vdd) in the resistance stack, as they are just future "access transistors". The resistors will be replaced with a magnetoresistive device later.
My issue now is that the clock is disrupting the signal that the comparator itself has to process. This can be seen in v1 and v2. As a whole the comparator seems to be working. But my device I use instead of the resistance, will be sensitive to these glitch and can behave unexpectedly.
How can I solve this?
As you can see I am comparing the voltages across two resistors that are clamped up using some MOSFETs. Please ignore the bottom MOSFETs (gate connected to vdd) in the resistance stack, as they are just future "access transistors". The resistors will be replaced with a magnetoresistive device later.
My issue now is that the clock is disrupting the signal that the comparator itself has to process. This can be seen in v1 and v2. As a whole the comparator seems to be working. But my device I use instead of the resistance, will be sensitive to these glitch and can behave unexpectedly.
How can I solve this?