surerdra
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i need to take 24 bit data from ads1271 ic , it need some control signals through fpga, while i trying to generate sync signal it depends on dout of ic.
the output of ic is 24 bit data through dout.
when data availble in dout it is high, then sync low(after 1 clk period it will high) as early as dout return to low, from that on wards for every falling edge of clk we take 24 bit data from dout to registe, again when 24 bit data availble on dout it will goes high.
--the loop is continue---
i implement vhdl code for that , but failed.
please give some hint about programing
the output of ic is 24 bit data through dout.
when data availble in dout it is high, then sync low(after 1 clk period it will high) as early as dout return to low, from that on wards for every falling edge of clk we take 24 bit data from dout to registe, again when 24 bit data availble on dout it will goes high.
--the loop is continue---
i implement vhdl code for that , but failed.
please give some hint about programing