Commonly used VCO frequencies

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Hi Guys,

As an exercise, I am thinking of designing a VCO with Cadence. What are some commonly used/popular VCO specs. I can design for? Is the cell phone (900 MHz) a good frequency I can use to design a VCO for? Eventually I want to use this VCO in a PLL. I am doing this to get some IC design exposure for a job interview.

Thanks.
 

Depents upon target process,
2.4GHz may be another good choice.
Maight want to check phase noise at 1MHz offset.
 

I want to use 0.35 micron.

So if I tried a 2.4GHz VCO, what VCO architecture should I use?

I searched and found some tutorials here but can you point me to some more tutorials for designing a 2.4GHz VCO?

Appreciate your help.
 

At 0.35u, I'm afraid you cant design a 2.4GHz VCO. Try a 1GHz VCO rather.
You can design a current starved single ended ring (3 inverter structure) to start with a simple and low power VCO.
 

Thanks, saro_k_82.

What are some realistic specifications for 1GHz VCO design? I want to write the specs. up before I start designing.

Also I read a paper that showed at 2.4 GHz, they had used an LC oscillator with a differential CMOS circuit for negative resistance. Is that a good design for 1 GHz, 0.35 um process?

Also I would like to add some DFT in my VCO design. Is that possible? How?

Appreciate your help.
 

LC oscillators make sense only for higher frequencies (beyond 5GHz). At 1GHz the size of the components would prohibit their usage even though they exhibit very good Q.
Go for a single ended ring and target around -85dBc/Hz at 1MHz offset
 

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