Common source amplifier design across corners

[diarmuid]

Hello,

As part of a larger block I am working on, I need to insert a simple common source amplifier.
I am using an NFET as the driver biased up using a cascoded PMOS current source.

At typical corner I bias the amp to achieve the required output DC bias. However, across
corners the output DC bias goes bananas!

For example:

- at Fast N/slow P corner the output DC bias drops, pulling my NFET driver out of saturation.
- at slow N/fast P corner the output DC rises, pulling the PMOS current source out of saturation hence starving
the amp of any current.

Needless to say, at both corners my nominal gain (42dB) goes to near zero.

Does anyone have an idea as to how to bias a common source amp such that it will hold its gain close
to its nominal value across corners?

Any input greatly appreaciated!

Thanks,

Diarmuid

 

[kemiyun]

That's a nice thing to mention and the answer depends on what you are trying to do, as always.

If you are going to implement this thing as an open loop amplifier, you have serious problems. You need to find a method to ensure that the output voltage will be at the desired DC bias. Since your gain is 42 dB, if you have a 1 V supply, a 10 mV threshold voltage change, might cause your output to hit the rail. So you shouldn't, ever, bias your current sources or input transistors with VDC. You should bias them using a current source and a mirror. Even then, your output can be saturated, if so you should start considering a translinear loop to really stabilize the output voltage. Another thing is providing the distribution to the IC user to let them decide how to bias it, if this is going to be only an open loop amp. You can find such approach in ADC datasheets, they provide SNR vs common mode voltage and let the user decide the common mode. It is not the same but similiar.

If you are asking for simulations, the first advice can be applied. Other than that, even if you are going to use it open loop, you can close the loop, extract the biasing points generated by the loop, feed them to the circuit under test via ideal buffers and measure the circuit. This is basically how you simulate an opamp, because the first approach won't work for opamp since the gain is extremely high.

Worst thing you can do is running a DC sweep for each corner, and deciding what voltages you should apply to get a certain output voltage.

 

[diarmuid]

Thanks Kemiyun for the response.

2 questions:

1. What do you mean by "VDC"?

2. As a current mirror is essentially a translinear loop, are you referring to a more typical translinear loop you would find in a class AB output stage?

Thanks,

- - - Updated - - -

... do you have an example of any particular translinear loop which may be useful?

 

[kemiyun]

1- I meant just putting a voltage source to bias a circuit. That's not going to work.

2- For simulation purposes you shouldn't create a translinear loop just to measure it. You should just establish a DC bias. I wrote that to point out that if you are going to come up with a product like "42 dB amplifier" you should know and force your output DC bias.

To make it more clear, closing the loop to create DC biasing is the most common method for simulations. If you have high gain, even 1 mV will saturate your output. So closing the loop is a solution. Or you can just force the output node to a DC level by connecting a DC voltage through an extremely high inductance.