Common path in Clock tree synthesis (CTS)

Common clock path in Clock tree synthesis (CTS)

Hello all,

is there any command in ICC or Olympus-SOC to control buffers added to common clock path (of launch clock path and capture clock path) during CTS(clock tree synthesis)

Thank you.


OR any other way to control buffer insertion in common clock path?

Yes there is. You can do this by specifying insertion delay for a clock domain.

Thanx for reply pavanK.

As you know, insertion delay is the time taken for the signal to propagate from the clock root pin to leaf clk pin.
And insertion delay directly proportion to clock tree levels, am i right?

In that case if i increase insertion delay then clock tree levels are increase, and which may create other issue like power consuption, routing congestion etc, right? And obviously for better timing, who have to keep insertion delay as minimum as possible.

so, my question is now, suppose no. of buffers inserted on launch clock path are 6 and on capture clock path are 7 including common path. but there are only 1 or 2 buffers on common path. In that case can i increase number of buffers on common path (from 1 or 2 to atleast 4) by keeping insertion delay nearly same.

I guess if ur keeping the logic together close enough the tool might try to put buffers in the common path.
Also the CG cells placement matters here.

If u have to split the logic group to two u can make two branches of CTS.
This might also help.

Thanx pavanks..

I have another query that when i saw my timing report, i found that there are 3 buffers placed in common clock path but delay corresponding to launch path and capture path was different..
How that is possible? In launch path, delay till these 3 buffer is 356ps and for same buffers in capture path it showing 266ps. these three buffers are part of common path.

If anyone know reason behind this, then please replay..

Have you switched CRPR on ?
If it is on it will subtract the diff of delay.
So that the delay of the common path is same.