[SOLVED] Common Mode Feedback Stability Analysis

[fhongjin]

Hi all,
I am trying to do a common mode stability analysis for a fully differential operational amplifier in Cadence. The opamp is used to build an integrator.I set up my testbench as follow:

However,the stb analysis result I got is like this:

I checked the dc operation point of my transistors and they look fine. The output common mode voltage matches the reference voltage as well.

I also tried to directly short the cap I placed across the opamp. The result of stb is also weird. Could someone lecture me a lil bit on how to correctly perform a common mode stb analysis please?

Thanks in advance for your help!!

 

[FvM]

Please show a schematic that clarifies where the CM feedback path is.

 

[fhongjin]

Please show a schematic that clarifies where the CM feedback path is.

Hi FvM,
I do not have the schematic right now (My laptop is broken for the moment). But I want to confirm that do I need to break the differential feedback loop when simulating stb of the common mode feedback loop?

 

[FvM]

Hi FvM,
I do not have the schematic right now (My laptop is broken for the moment). But I want to confirm that do I need to break the differential feedback loop when simulating stb of the common mode feedback loop?

Basically yes, but CM feedback path is usually implemented internally of the true differential amp. If so, it can't be probed at the shown position.

 

[Leplace]

If X56_IO2/X59_IO2 are the CMFB points from output, then the position of cmdmprobe is incorrect, 'Cause cmdmprobe not in the CMFB loop.