fhongjin
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Hi all,
I am trying to do a common mode stability analysis for a fully differential operational amplifier in Cadence. The opamp is used to build an integrator.I set up my testbench as follow:
However,the stb analysis result I got is like this:
I checked the dc operation point of my transistors and they look fine. The output common mode voltage matches the reference voltage as well.
I also tried to directly short the cap I placed across the opamp. The result of stb is also weird. Could someone lecture me a lil bit on how to correctly perform a common mode stb analysis please?
Thanks in advance for your help!!
I am trying to do a common mode stability analysis for a fully differential operational amplifier in Cadence. The opamp is used to build an integrator.I set up my testbench as follow:
However,the stb analysis result I got is like this:
I checked the dc operation point of my transistors and they look fine. The output common mode voltage matches the reference voltage as well.
I also tried to directly short the cap I placed across the opamp. The result of stb is also weird. Could someone lecture me a lil bit on how to correctly perform a common mode stb analysis please?
Thanks in advance for your help!!