Common DRCs and possible solutions

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Hi all,

Can someone give me a list of common DRCs that can see in Layout and the fixes for it ?

quickly coming out of my head,

1. spacing issue( metal to metal, well to well)
2. antenna effect
3. metal density

can someone continue the list here? also can you provide possible solutions too?

Thanks in advance !!
 

Hi

This is kind of a though job to list all types of DRC errors that could occur. Depending on the technology node you are using, and the models provided by the foundry, you can get additional errors.
Typical ones are:

- Layer min widths (Metal, poly, active areas, np, pp,...)
- Layer spacings
- Layer overlaping to another layer
- metal densities, active area densities
- via stacking (on some technologies)
- Wide metal sheets
- Substrate and well taps (pwell & nwell connections next to active areas)
- antenna effect (although can be in different error check run)
....

For more info, i suggest you to check the DRC documentation.
 


Hi,

There are different kind of DRCs depending on the Technology that you are going to work on. As you go into lower technologies the number of layers that are going to be used and the DRCs to be satisfied will get complex.

1. Min and Max width of Different layers (Metal, Poly, Diffusion etc.,)
2. Min and Max spacing between different layers
3. Dimensions of VIA and Contacts
4. Min area of different layers (Metal, Diffussion, N-well)
5. N-Implant, P- Implant, Vt layer, N-well DRCs which will include min area, abutment, Overlap, spacing and width)
6. Dummy poly width and spacing DRCs
7. LUP- Latch-up (Related to substrate or body connection)
8. Density DRCs


You can refer DRM from respective foundry for detailed information
 

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