That I know there is no predefined way to get the smallest delay. You give the constraints and the tool will run until it matches all constraints or gives up. Then it stops. If the constraints are too easy it will finish quick. So, it will probably be keep on tighting it until it fails.
I remember some time back for on DC Infineon used to do something like this for area. They would synthesize the design, get the resulting area, then set_max_area to the result - 10% and then run the tool to reduce it even more.
Keep in mind that once you add your driver and load capacitance it will get a bit worse. And of course, keep in mind that this minimum delay does not come for free. The tool had to work harder to speed up the circuit. This could mean it used bigger buffers, perhaps duplicated some logic, perhaps use lower VT cells (if you have more than one VT library loaded), and then that could mean you gained speed but lost in area and power consumption.