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Command for dumping every signal and variable in VCS

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khaledismail

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Hi all,

When tracing the drivers for signals in a DVE waveform, I notice the below message in "Tooltip Viewer":
"Possibly active driver (analysis was incomplete due to missing dump, dynamic variables or internal limitations)"

I notice that I also can't show some wires, regs and other SystemVerilog variables on the DVE waveform.
What command should I use in VCS to dump all possible wire, reg and variable so I can plot them all in DVE?

Thanks.
 

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