rakeshk.r
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Hi, I have two questions.
1. Are there alternative methods to implement a combinational logical shifter similar to 'srl' and 'sll' syntax available in VHDL ?
2. I was curious to check the power consumption between these two design of shifters which I have implemented in VHDL. Note! Both these codes shown below are not meant for the same functionality.
and
Before viewing the synthesis reports, I was expecting the entity named 'r_shifter' to consume more power due to the extra logic implemented in the shifter design compared to the entity named 'rshift_v1'. However both consumed same amount of power. It doesn't make sense to me, could some enlighten me if my thought was wrong ? I am using Synopsys DC to obtain the power consumption results from the synthesis report. Thank you.
1. Are there alternative methods to implement a combinational logical shifter similar to 'srl' and 'sll' syntax available in VHDL ?
2. I was curious to check the power consumption between these two design of shifters which I have implemented in VHDL. Note! Both these codes shown below are not meant for the same functionality.
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY r_shifter IS
GENERIC(
w_i : positive := 16;
w_o : positive := 16;
wdl : positive := 4
);
PORT(
input : IN unsigned (w_i-1 DOWNTO 0);
output : OUT unsigned (w_o-1 DOWNTO 0);
shifts : IN unsigned (wdl-1 DOWNTO 0)
);
END r_shifter ;
--
ARCHITECTURE logical OF r_shifter IS
BEGIN
lshifter : process(input, shifts)
variable reg1 : unsigned(w_i-1 downto 0);
begin
if w_i > w_o then -- input is n+1 bits
reg1 := input srl to_integer(shifts);
output <= reg1(w_i-2 downto 0);
else
output <= input srl to_integer(shifts);
end if;
end process;
END ARCHITECTURE logical;and
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY rshift_v1 IS
GENERIC(
w_i : positive := 16;
w_o : positive := 16;
wdl : positive := 4
);
PORT(
input : IN unsigned (w_i-1 DOWNTO 0);
shifts : IN unsigned (wdl-1 DOWNTO 0);
output : OUT unsigned (w_o-1 DOWNTO 0)
);
END rshift_v1 ;
--
ARCHITECTURE logic OF rshift_v1 IS
BEGIN
shifter_v1 : process(input, shifts)
begin
output <= input srl to_integer(shifts);
end process;
END ARCHITECTURE logic;