[SOLVED] combinational shifters in VHDL

[rakeshk.r]

Hi, I have two questions.

1. Are there alternative methods to implement a combinational logical shifter similar to 'srl' and 'sll' syntax available in VHDL ?

2. I was curious to check the power consumption between these two design of shifters which I have implemented in VHDL. Note! Both these codes shown below are not meant for the same functionality.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY r_shifter IS
   GENERIC( 
      w_i : positive := 16;
      w_o : positive := 16;
      wdl : positive := 4
   );
   PORT( 
      input  : IN     unsigned (w_i-1 DOWNTO 0);
      output : OUT    unsigned (w_o-1 DOWNTO 0);
      shifts : IN     unsigned (wdl-1 DOWNTO 0)
   );

END r_shifter ;

--
ARCHITECTURE logical OF r_shifter IS
BEGIN
lshifter : process(input, shifts)
variable reg1 : unsigned(w_i-1 downto 0);
begin 
  
  if w_i > w_o then  -- input is n+1 bits
    
      reg1 := input srl to_integer(shifts);
      output <= reg1(w_i-2 downto 0);
    
    else
      
      output <= input srl to_integer(shifts);
      
  end if;      
 
end process;
END ARCHITECTURE logical;

and

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY rshift_v1 IS
   GENERIC( 
      w_i : positive := 16;
      w_o : positive := 16;
      wdl : positive := 4
   );
   PORT( 
      input  : IN     unsigned (w_i-1 DOWNTO 0);
      shifts : IN     unsigned (wdl-1 DOWNTO 0);
      output : OUT    unsigned (w_o-1 DOWNTO 0)
   );

END rshift_v1 ;

--
ARCHITECTURE logic OF rshift_v1 IS
BEGIN
shifter_v1 : process(input, shifts)
begin
  
    output <= input srl to_integer(shifts);

end process;  
END ARCHITECTURE logic;

Before viewing the synthesis reports, I was expecting the entity named 'r_shifter' to consume more power due to the extra logic implemented in the shifter design compared to the entity named 'rshift_v1'. However both consumed same amount of power. It doesn't make sense to me, could some enlighten me if my thought was wrong ? I am using Synopsys DC to obtain the power consumption results from the synthesis report. Thank you.

 

[FvM]

Presumed both designs implement the same logic function, they can be expected to be mapped to the same gate level hardware independent of the design entry details. Unless commanded differently by specific constraints.

That's how a synthesis tool works.

 

[rakeshk.r]

When you say 'design entry details' , what do you mean ? In the component, 'r_shifter' , I think the logic contains a comparator, multiplexer unlike in the other component. So shouldn't it cost extra resources ?

 

[FvM]

the logic contains a comparator, multiplexer

That's nothing but a way to describe logic function (or "design entry"), not necessarily related to implementation. The design compiler breaks up any combinational logic into a truth table and synthesizes it with the available hardware elements.

 

[rakeshk.r]

What about my first question. What is the usual/better way to implement a combinational shifter other than using 'srl' and 'sll' ?

 

[xtcx]

Hi, I have two questions.

1. Are there alternative methods to implement a combinational logical shifter similar to 'srl' and 'sll' syntax available in VHDL ?

2. I was curious to check the power consumption between these two design of shifters which I have implemented in VHDL. Note! Both these codes shown below are not meant for the same functionality.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

ENTITY r_shifter IS
   GENERIC( 
      w_i : positive := 16;
      w_o : positive := 16;
      wdl : positive := 4
   );
   PORT( 
      input  : IN     unsigned (w_i-1 DOWNTO 0);
      output : OUT    unsigned (w_o-1 DOWNTO 0);
      shifts : IN     unsigned (wdl-1 DOWNTO 0)
   );

END r_shifter ;

--
ARCHITECTURE logical OF r_shifter IS
BEGIN
lshifter : process(input, shifts)
variable reg1 : unsigned(w_i-1 downto 0);
begin 
  
  [B][COLOR="#FF0000"]if w_i > w_o then  -- input is n+1 bits
    
      reg1 := input srl to_integer(shifts);
      output <= reg1(w_i-2 downto 0);
    
    else[/COLOR][/B]
      
      output <= input srl to_integer(shifts);
      
  end if;      
 
end process;
END ARCHITECTURE logical;

Before viewing the synthesis reports, I was expecting the entity named 'r_shifter' to consume more power due to the extra logic implemented in the shifter design compared to the entity named 'rshift_v1'. However both consumed same amount of power. It doesn't make sense to me, could some enlighten me if my thought was wrong ? I am using Synopsys DC to obtain the power consumption results from the synthesis report. Thank you.

The highlighted statement will be ignored by the synthesis because the condition will never be true as this is fixed as constant. And hence both the code are the same. This is what FVM mentioned.

 

[TrickyDicky]

The highlighted statement will be ignored by the synthesis because the condition will never be true as this is fixed as constant. And hence both the code are the same. This is what FVM mentioned.

It could be true if the user set the generics up that way when they instantiate the entity - the generics at the top of the file are given default values in case the user does not assign them when instantiating it.

But it is true that the logic is the same for both peices of code.