combinational logic before synchronizer

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sumanth495

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hi every one...
presently i am working on Questa CDC analyzer..
while running the tool, i am getting some violations
violation (1). combinational logic before synchronizer.
before synchronizer i am using one 2 input "OR" gate. both inputs are coming from clk1 domain.
my synchronizer is working in clk2 domain.
Now what is the solution for this violation?

i have one more doubt.. what is the solution for single source reconvergence(SSR) violation ?
 

remove the or gate from cdc path and put if after the synchronizer.
 

hi tariq,
if i move that "OR" gate after synchronizer, then i need to use 2 synchronizers right?
then number of synchronizers will increase..
Is this the only solution or is there any other solution?

---------- Post added at 14:00 ---------- Previous post was at 13:57 ----------

i got one more idea...
as these two inputs for OR gate, are from same clk domain. (that signals will be changed at same time). so can we neglect this violation?
If not so, can any one plz suggest me the proper solution for this?
thanks in advance
 

I think that the risk with the design is that a '0' glitch will propagate thru the syncronizer if the inputs to the OR gate change from 01 to 10.
This risk is not eliminated if a syncronizer is added and the OR gate is moved to the clk2 domain.
The safest solution should be to add a dff after the OR gate, in the clk1 domain.
 
i agree with std_match.

Thanks for the insight
 

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