Combination of analog and digital in cadence

[Girish Achary]

we are using combination of auxiliary and charge scaling DAC for efficient DAC in SAR ADC implementation. We are designing this in cadence viruoso(180nm technology) and writing program for SAR in digital mode. Can you please suggest me how to give digital o/p to analog input.

 

[erikl]

... how to give digital o/p to analog input.

What's the problem? Different supply voltages? Then use level shifters!

 

[checkmate]

2 ways of going about it.
1. Synthesize the digital code, do a technology mapping, and then instantiate the structural model of the digital code into the analog simulation.
2. Use a mixed signal simulator.

 

[analog-designer]

Compile your hdl code in 5x structure. (e. g.ncvhdl -use 5x) for checking for errors and including in cds.lib. If your code is available in library manager though cds.lib you can create a config cell and choose the right cell view in hierachy editor. After this you can simulate this config cell in ADE in ams mode.

 

[steadymind]

1) As Erikl mentioned you need levelshiters at the end of your Digital O/P to your analog Inputs.
2) to run a mixed mode sim, you can select a suitable connectLib, which will perform the necessary voltage domain transitions.
If you are taping this chip out i would prefer using levelshifters to check.