Code for combination module in the sequential circuit

tarkyss · Sep 8, 2005

for a combination module in the sequential cirtuit,
verilog code like below is ok? is there any problem?
always @( reset or a or b)

AlexWan · Sep 8, 2005

about reset

Hi tarkyss,

Why to use reset signal in your combination module?

If you use the reset as enable signal, you may use another singal to connect this module.

omid219 · Sep 8, 2005

about reset

From the RTL coding points of view, it is OK. But if you mean it is a good design practice or not, it depends to your design and what you want to do with reset in your combinational logic.

tarkyss · Sep 8, 2005

Re: about reset

because a counter is needed to count the pulse of a signal,
so i must give a initial value before count.
another questions i am afraid the counter will introdue latch.
but if dont use counter, how to implement the funtion that count the pulse of a signal.

echo47 · Sep 8, 2005

about reset

Here is a basic counter.

Code:

module top (clk, reset, count);
  input             clk, reset;
  output reg  [7:0] count;

  always @ (posedge clk or posedge reset) begin
    if (reset)
      count <= 0;
    else
      count <= count + 1;
  end
endmodule

tarkyss · Sep 8, 2005

about reset

echo47, if i can implement it with clock, i would not ask for help here

echo47 · Sep 8, 2005

about reset

You question is too unclear. Please give more information.

"always @( reset or a or b)" is a valid way to start a verilog block.

tarkyss · Sep 8, 2005

about reset

no clock
t is input
w is output
every the nth( n may be 1 2 4 t becomes high level,
w output a high level, the width is the same with t
always @( reset or t )
if( Reset )
begin
counter = n;
w= 1'b0;
end
else
begin
if( t )
begin
counter = counter + 1;
if( counter == n)
w = 1'b1;
end
else
begin
w=1'b0;
if( counter == T )
counter = n;
end
end
reset is a global asy signal , put it in always list with other normal signal , is there any problem?
if i dont want to introduce latch, how can i code?
thanks

omid219 · Sep 8, 2005

about reset

Without having a latch, how can you keep the counter's value?
I think the latch is the only way and you can use the reset in always block.

tarkyss · Sep 8, 2005

about reset

if use reset as above, do it cause reset signal unclear?

omid219 · Sep 8, 2005

about reset

what do u mean by unclear reset? When you are doing an asyc design and using latch, you have to make sure you do not have any glitch or transition when the latch's gate is open, if the reset and other signals are stable, then you can use them that way.

echo47 · Sep 8, 2005

Re: about reset

The "t" input looks like a clock. You seem to be trying to use asynchronous syntax to do a mostly synchronous job. That can give a variety of unexpected problems. It's better to use synchronous logic wherever possible.

I'm not sure I understand the desired behavior, but how about this?

Code:

module top (reset, t, n, w);
  input             t, reset;
  input       [3:0] n;      // any value from 1 through 9
  reg         [3:0] counter;
  output            w;      // output one pulse of width t for every t input pulses

  assign w = ~counter[3] & t;

  always @ (negedge t or posedge reset) begin
    if (reset)
      counter <= 0;
    else
      counter <= (counter == 0) ? 1 - n : counter + 1;
  end
endmodule

Here's a ModelSim output with n=4, and then changing to n=2:

tarkyss · Sep 8, 2005

Re: about reset

echo47 said:
thank you very much
The "t" input looks like a clock. You seem to be trying to use asynchronous syntax to do a mostly synchronous job. That can give a variety of unexpected problems.
what problem ? for example? It's better to use synchronous logic wherever possible.

I'm not sure I understand the desired behavior, but how about this?
yes

Code:

module top (reset, t, n, w); input t, reset; input [3:0] n; // any value from 1 through 9 reg [3:0] counter; output w; // output one pulse of width t for every t input pulses assign w = ~counter[3] & t; always @ (negedge t or posedge reset) begin if (reset) counter <= 0; else counter <= (counter == 0) ? 1 - n : counter + 1; end endmodule

Here's a ModelSim output with n=4, and then changing to n=2:

the above code will generate a flip-flop, and the t is connect to the clk port of flip-flop, is it ok? and would introduce any problem? the whole system is syn, but the block i said is of no clk and is combination logic.

echo47 · Sep 8, 2005

about reset

I think the name "t" is throwing you off track. If you simply rename "t" to "clock", then you will see that this is an ordinary synchronous project, except for the AND gate at the "w" output. (Unless I misunderstood the project requirements.)

If you try to implement a binary counter using asynchronous logic, you must be extremely careful or else the synthesizer will generate hazards and races that cause erratic counting in the target device. A gray counter would help, but still that's a clumsy approach.

Yes, you want the synthesizer to use real flip-flops connected to a low-skew clock distribution net (probably named "t").

tarkyss · Sep 8, 2005

Re: about reset

i am sure t is not clock, the period is not fixed, the time between two high pulse is not fixed

echo47 · Sep 8, 2005

about reset

That's fine. A clock that varies in period is still a clock. Synchronous logic and asynchronous logic don't care what the period is, unless it exceeds the speed of the chip.

checkmate · Sep 8, 2005

Re: about reset

You are right that echo's code synthesizes to a flipflop. But the fact that there are no other input signals that are asynchronous wrt t (with the exception of reset which has been handled), the flipflop performs identically to a latch.

You can of course alternatively code a latch.

Code:

module top (reset, t, n, w); 
  input             t, reset; 
  input       [3:0] n;      // any value from 1 through 9 
  reg         [3:0] counter; 
  output            w;      // output one pulse of width t for every t input pulses 

  assign w = ~counter[3] & t; 

  always @ (t or reset) begin 
    if (reset) 
      counter <= 0; 
    else if (t)
      counter <= (counter == 0) ? 1 - n : counter + 1; 
  end 
endmodule

Just to note that this code is less efficient for simulation purposes compared to echo's one as the always block is triggered more frequently, ie during falling edge of t and reset.

p.s. please use the code tags for the benefit of others.

echo47 · Sep 8, 2005

about reset

checkmate - that needs to be "else if (~t)" because I originally used negedge.

That works fine in behavioral simulation, but post-route simulation (Xilinx Virtex-II) is a mess, probably due to clock skew problems. I see counter bits oscillating at about 1 GHz. The place-and-route software emitted various warnings, telling me I was attempting to do dumb things.

Do you know if there are ways to make this work? Just an academic question - I would normally never attempt this.

Similar discussion in another thread:

beckchm · Dec 22, 2005

Re: about reset

your code is not so good .

Code for combination module in the sequential circuit

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