moisiad
Member level 4
![Member level 4](/styles/images/ranks/dlevel4.gif)
Hi all
I am doing analog design in cadence enviroment using Spectre. Can you please inform me how can i simulate analog cells (in transistor levels) along with digital cells (in verilog). I assume that the difficulty is to translate the logical levels of the digital cells in analog signals recognisable from the analog part.
Thanks
I am doing analog design in cadence enviroment using Spectre. Can you please inform me how can i simulate analog cells (in transistor levels) along with digital cells (in verilog). I assume that the difficulty is to translate the logical levels of the digital cells in analog signals recognisable from the analog part.
Thanks