CMOS weak inversion design matching

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I am studying CMOS weak inversion design. I know the matching in weak inversion is very poor, so we need to use large size of transistors in order to improve the matching. But I don't know how large is enough. For example, in the IC industry, a differential pair in weak inversion should have what size of width and length? Anyone could give me some suggestions? Many thanks.
 

no one could give some suggestions?
 

That depends upon process PDK. They will give a sigma(vt). You can use that to design. Typically this is given for strong inversion. You should ask them if they recommend the same value for weak inversion
 

Well, for an 0.18um process, i want to know what order of MOS size is normally needed to ensure the matching in the weak inversion design for a differential pair. The size W*L is in 10um^2, or 50um^2, or 100um^2, or 200um^2, or even more?
 

At weak inversion and small geometry the channel charge can
be single carrier or few carriers. Random dopant density variation
becomes a problem.

I believe this question wants data, not generalizations. Other than the
usual "more area is better", which is true but not entirely useful
because you really want to know the point of diminishing returns,
something that is likely to vary with the inversion strength if you
are indeed up against dopant variation or surface states' variability.

And of course those variabilities vary with each lot....
 

you can see this file.
it is a workshop on weak inversion operation.
 

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