CMOS two stage amplifier in cadence

I have been given a two stage amplifier design to create in cadence. I have worked out how to create the schematic, but can't really get any further.



I have to calculate the small signal gain, the 3db bandwidth and the dc gain. The only instruction I have is 'make use of the calculator in cadence. Remeber to check the DC operating points.'

I have worked out how to use the calculator I think, I have got my node voltages up. Obviously now I need to fine tune the circuit.

Does anyone know of a tutorial that could walk me through these steps of tuning? Or could someone break it down a bit more so I can try and work it out?

Thanks.

First of all Q8 should be diode connected. In miller compensated two stage opamp has three groups of transistors. In your case a three groups of transistors exists. An input differential pair, an nmos current mirror made by Q3, Q4 and Q7 and second pmos current mirror made by Q8, Q5 and Q6.

The dimensions of each transistors should be matched to current ratios between the branches.

Dominik Przyborowski said:

First of all Q8 should be diode connected. In miller compensated two stage opamp has three groups of transistors. In your case a three groups of transistors exists. An input differential pair, an nmos current mirror made by Q3, Q4 and Q7 and second pmos current mirror made by Q8, Q5 and Q6.

The dimensions of each transistors should be matched to current ratios between the branches.

Click to expand...

Thanks Dominik,

I spotted the error with Q8. The amplifier is working and I have worked out how to measure gain and phase etc, however, I now want to maximise the gain by playing with transistor sizes. Is there a good method for doing this?

Thanks.

In strong inversion gain is inversly proportional to square root of drain current. For very high gain you need long channel current sources and high gm of input pair (biased in moderate inversion). Of course longer channels → smaller transconductance → higher capacitances → lower bandwidth.

Dominik Przyborowski said:

In strong inversion gain is inversly proportional to square root of drain current. For very high gain you need long channel current sources and high gm of input pair (biased in moderate inversion). Of course longer channels → smaller transconductance → higher capacitances → lower bandwidth.

Click to expand...

Thanks, I see the square root relationship, so, and that increasing channel length will reduce the current. I guessed decreasing Width by the same factor would do the same. So I tried decreasing the W/L ratio of all the diff amp stage transistors by 50% (I reduced the number of gates by half), but my gain remained the same with a small reduction in bandwidth!

But then I see that decreasing the W/L ratio by decreasing W, decreases gm! Because gm depends on the square root of both W/L and the drain current.

It all seems to contradict each other!

Your Gain = A₁ × A₂

A₁ = g_m,Q1Q2 × r_o,Q2||r_o,Q4

A₂ = g_m,Q7 × r_o,Q7||r_o,Q6

Since r_o,n < r_o,p for similar conditions, Your A₁ is most likely limited by the r_o,Q4

So use min length for the input pair to maximize their g_m.
Use higher length for the NMOS current mirror load to increase its r_o

For the second stage try playing around with the current by sizing Q6 to get to the sweet spot with the highest gain. This is just a basic CS stage and equations for it are available.

In a few iterations of playing around with the sizes, you would be able to get a good gain.

You would have to use a Miller Capacitance to make sure that your Amplifier is stable.

Thanks for the explanation it really helps. however, why is the output resistance of an n higher than the p if they both have the same current? I thought ro was 1/(lamda*ID), which would make them the same?

I can understand that it would be beneficial to increase gm though, and that it can be achieved by increasing the aspect ratio. Is there any reason to choose to reduce L instead of increasing W? Is it to do with avoiding the increase in capacitance?

--- Ok, so I thought I understood it and that reducing L of Q1 and Q2 would increase gm and thus increase the gain. Yet by sweeping values of L from 0.6u to 1.2u I see that completely the opposite is true! So it seems to increase gain I should increase L? Decreasing the length seems to damage ro disproportionatley to what it increases gm.

BartlebyScrivener said:

Thanks for the explanation it really helps. however, why is the output resistance of an n higher than the p if they both have the same current? I thought ro was 1/(lamda*ID), which would make them the same?

Click to expand...

Output Resistance of NMOS is LESS than that of PMOS. This has to do with mobility and what not. This term is hidden in the I_d part since for same current, PMOS would have more V_gs for the same size.

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BartlebyScrivener said:

I can understand that it would be beneficial to increase gm though, and that it can be achieved by increasing the aspect ratio. Is there any reason to choose to reduce L instead of increasing W? Is it to do with avoiding the increase in capacitance?

Click to expand...

It is mainly because lowest L would easily maximize the gm. Increasing W/L with higher L would mean more size and hence more cap. If you are not limited by the cap size then you can as well go for higher L.

BartlebyScrivener said:

--- Ok, so I thought I understood it and that reducing L of Q1 and Q2 would increase gm and thus increase the gain. Yet by sweeping values of L from 0.6u to 1.2u I see that completely the opposite is true! So it seems to increase gain I should increase L? Decreasing the length seems to damage ro disproportionately to what it increases gm.

Click to expand...

When you sweep L, what do you do with the W? If the Input pair goes in subthreshold for high W/L then it would not give you any advantage by further increasing the W/L since gm would remain the same.
I guess that in your output resistance equation for your first stage, r_on||r_op, rop is less than ron which is why you see a an increase in gain with increase in L and like I said before if your input pair is close to subthreshold, the change in gm with increase in L would be very small but the change in r_o would be big and hence you would see a big gain.