cmos technology- nmos/ pmos

1) how does the gate oxide thickness affect the performance (channel conductivity, subthreshold leakage) of mosfet?
2) If there is gate oxide (insulator) between the gate and the P-substrate(body of Nmos) then how can the conduction channel between the two n wells be formed?

Check this link, I think it will help.
CMOS - Wikipedia, the free encyclopedia

In MOS, when Gate voltage is above threshold voltage, conduction takes place between source and drain. Source and drain regions are heavily dopped regions. NMOS is fabricated in the P substrate. When gate voltage is less than threshold voltage, the current flow between source and drain is effectively zero because a few carriers are available for conduction(Substrate is lightly dopped). When gate voltage is increased from Zero it starts repelling hole from the surface of substrate below oxide layer. Holes are majority charge carriers in P type semiconductor. Positive potential on gate repels hole. The region below oxide is depleted from carriers. Remember electric field can penetrate through insulator also. But when a significant potential is applied to gate it repels hole from surface and attracts electrons on surface. There electrons form a very thin conducting layer on surface. There are lot carries available for conduction.

For details please read (one of the following):
1. Chapter 3, CMOS Digital Integrated Circuits by Sung-Mo Kang
2. Chapter 2, CMOS VLSI Design- A Circuit and System Perspective by Neil H.E. Weste
3. Device physics by RS Mullar

see the attachment