cmos schmitt trigger QnA

• Yes Either all Pch are ON or all Nch are On.
• The ratio |Vgs/Vgs(th)|= 1 to 2 and Ron is fairly high impedance for Vy andVz during transition. Est. 1k to 50k, but not floating.
• The transition of Vy and Vz is related to the Vgs(th) aka Vt threshold.
• Vy and Vz are not floating because M3, M6 are driven by the output.
• I believe Vt tends to be 1/3 of Vdd. for Vdd= max Vdd or 5V whichever is lower.
• The wide tolerance of Vt controls the hysteresis of VIL and VIH.
• While "out" is high and the input is below VIH and rising in this oscillator, the PFETs are active and Vy is tracing the Vgs from the threshold of the NFETs to the OFF threshold of the PFETs.

Shown above the Schmidt Trigger is used as an astable oscillator with feedback R and input C. As the input voltage, Cin follows an integrated square wave between the hysteresis thresholds, ideally between 1/3 and 2/3

The output impedance will be higher than standard logic levels when the input is near Vdd/2 which makes this design sensitive for very low Vdd values when used as an Astable.

Do they make a 0.7V Schmidt IC this way? It would have to be buffered.

D.A.(Tony)Stewart said:

• 예를 들어 모든 Pch가 계속해서 모든 Nch가 켜져 있습니다.
• |Vgs/Vgs(th)|= 1 대 2의 핸들과 Ron은 전환 외에도 Vy 및 Vz에 대해 더 높은 이야기입니다. 동부표준시. 1k ~ 50k이지만 플로팅되지 않습니다.
• Vy 및 Vz의 전환은 Vgs(th)(일명 Vt 청년값)과 관련됩니다.
• M3, M6이 출력에 의해 구동되는 Vy 및 Vz는 부동 상태가 아닙니다.
• Vt는 Vdd의 1/3인 경향이 있다고 생각합니다. Vdd= 최대 Vdd 또는 5V 중 더 낮은 값.
• Vt의 넓은 범위는 V IL 및 V IH 의 히스테리시스를 제어합니다 .
• "out"이 입력이 V IH 에 있고 이 오실레이터에서 모집하는 동안 PFET는 활성 상태이고 Vy는 NFET의 청년 값에서 PFET의 OFF 청년 값까지 Vgs를 추적합니다.

View attachment 185481

대단한 슈미트가 피드백 R 및 입력 C가 있는 반응으로 사용됩니다. 입력 전압으로 Cin은 히스테리 군대 사이(이상적으로는 1/3과 2/3 사이)의 통합 휴대용파를 위해.

입력이 Vdd/2에 가까울 때 라우터는 표준 안정성보다 향상되는 이 설계는 Astable로 작동할 때 매우 작은 Vdd 값에 민감합니다.

이러한 식으로 0.7V 슈미트 IC를 만들까요? 회수해야 합니다.

Click to expand...

D.A.(Tony)Stewart said:

• Yes Either all Pch are ON or all Nch are On.
• The ratio |Vgs/Vgs(th)|= 1 to 2 and Ron is fairly high impedance for Vy andVz during transition. Est. 1k to 50k, but not floating.
• The transition of Vy and Vz is related to the Vgs(th) aka Vt threshold.
• Vy and Vz are not floating because M3, M6 are driven by the output.
• I believe Vt tends to be 1/3 of Vdd. for Vdd= max Vdd or 5V whichever is lower.
• The wide tolerance of Vt controls the hysteresis of VIL and VIH.
• While "out" is high and the input is below VIH and rising in this oscillator, the PFETs are active and Vy is tracing the Vgs from the threshold of the NFETs to the OFF threshold of the PFETs.

View attachment 185481

Shown above the Schmidt Trigger is used as an astable oscillator with feedback R and input C. As the input voltage, Cin follows an integrated square wave between the hysteresis thresholds, ideally between 1/3 and 2/3

The output impedance will be higher than standard logic levels when the input is near Vdd/2 which makes this design sensitive for very low Vdd values when used as an Astable.

Do they make a 0.7V Schmidt IC this way? It would have to be buffered.

Click to expand...

Thank you for explaining first.

I am studying to understand the Schmidt trigger circuit for IC's input noise.
The example is shown in the picture below.(this block diagram reference is 6EDL04I06PT(gate driver IC)

In the reference book, when the input is 0 as follows, the VZ node is defined as the VDD-VTN as follows.
Of course, this is not an important factor for the mechanism, but I didn't understand it.

Sorry, but I cannot explain this.

Vz refers here to the maximum voltage in my simulation. It is a node that joins M4, M5, M6.

2ϕF=-0.6V (?) means what? It must also apply to M5 and M6 equally as Vz is a node in cross-conduction between 0 & Vdd so Vz must be a ratio factor of Vt for M5 & M6.

Yet, it says Vz = Vdd minus Vt of M6 to be approximately equal to 3.5V.

Yet there is no mention of Vt,5 , which also affects Vz as much as Vt,6.

Perhaps, ask your Prof. and show him my simulation, then let us know, unless someone else can explain.

My thinking is more like, but not quite Vz = Vdd + Vt,6. -Vt,5 ,

I think you need to look at the VT stuff "at the point(s) of switching".
The Vgs of those FETs will wander and mostly be at zero current
when input is settled - but might be tens or hundreds of uA as
you cross over threshold and the built in contention (-> hysteresis)
does its part. I think the analysis is too simple. I've worked in some
SOI technologies where it's even worse, with body pumping and
"history effects" on the threshold you want to spec (but can't,
unless transition density is either super high (fully pumped to
quasi steady state) or super low (all bled out).

dick_freebird said:

I think you need to look at the VT stuff "at the point(s) of switching".
The Vgs of those FETs will wander and mostly be at zero current
when input is settled - but might be tens or hundreds of uA as
you cross over threshold and the built in contention (-> hysteresis)
does its part. I think the analysis is too simple. I've worked in some
SOI technologies where it's even worse, with body pumping and
"history effects" on the threshold you want to spec (but can't,
unless transition density is either super high (fully pumped to
quasi steady state) or super low (all bled out).

Click to expand...

I agree that one of the inactive nodes of Vy, Vz will have impedances higher than I stated.

But as the active node forces the output, the transitions of these nodes will still depend on M1 and M5 as well as M3 and M6. That sensitive to interference high-impedance node does not affect the thresholds because the other node is active asserts the output. When a rising input exceeds Vt on M5 , any noise on Vz should become attenuated but the rising switching threshold also depends on the Vt of M6.

The Vz threshold will then depend on M6's Vt threshold and the resistance ratios of each FET in a dynamic cross-conduction transition between M3&M6.