CMOS Sawtooth Waveform Generator

Hi guys, I have designed a simple sawtooth generator.

However, after doing the layout and extracted the parasitic capacitance and resistors I found that the sawtooth frequency as decreased.

Well, this makes sense of course. However I am afraid that I could have done a bad layout. I say this because, from what I have been taught and from what I learned from my experience is that the expected output from the extracted simulations does not differ VERY MUCH from the non-extracted simulations.

So, my sawtooth was trimmed for something around 500MHz and after the layout that value decrease too much, to something around 250/300MHz.

Is this normal? Can you guys clarify me, those who have done this kind of circuits?

Thanks in advance. Regards.

Could you provide more information on where you stand? What node are you on (65nm, 90nm, etc)? Also is it possible to provide a schematic for your design? By the looks of it, I would think you have some parasitic inductance somewhere, changing the center frequency.

Parasitic inductance? Or you meant parasitic capacitor?

With R extraction only, nothing change much. With C extraction I get that kind of deviation. With RC extraction I get almost the sme deviation.

The node is 130nm, the schematic is a simple opamp, with a capacitor connected to him in one pin and in the other a reference voltage to trip the comparator. The capacitor is charged by a current source.

Regards.

Parasitics sensitivity depends a lot on how big your timing
elements are (electrically) relative to the normal layout
parasitic baggage.

A sawtooth generator has some tough issues, like the
sharp edge particularly; the terminus of discharge, you
probably used some sort of comparator. Any overtravel
of the ramp (as would come from comparator loading lag)
will increase the total up-ramp travel by the down-ramp
overshoot (and with a strong discharge switch turned
off late, that overshoot could be significant).

I'd compare this aspect particularly to your schematic
design - is yout up-ramp slope as-designed, but the
down-slope just taking it too far into the weeds when
internal loading is applied?

This is why for PWM timing I prefer a triangle wave if no
hard simple sync scheme is needed. But sawtooth does
give you a nice "handle" for sync, where a triangle of the
sort I like, does not.

If you made the ramp bottom to zero, rather than a
comparator threshold, you could eliminate most of that
timing blow-out - so long as you can control the
discharge duration to be a trivial portion of the cycle
(possibly use a one-shot discharge, open loop discharge
dwell or even some sort of closed loop timing critique
that stays out of the main path, servoes the discharge
width slowly over time to maintain (say) a <50mV
valley but does not make that valley a piece of in-the-
now ramp timing cycle by cycle).

The slope of a sawtooth is recognized the retrace slope being >> the ramp slope. e.g. N times

This implies the bandwidth of the signal increases with this rate of return slope being e.g. N x 500MHz

This requires extremely low switch capacitance and controlled impedance for input and output.

A 500MHz sawtooth design is not simple.

Hi all and thanks for the reply.

In a matter of facts, I managed to design that sawtooth generator. However I found that problem after doing the layout.
What I did was to keep the layout as simple as possible, straighforward connections (without much L curves) and by tunning some components.

The reason I asked that was to ascertain how people do when they cross with a problem like this.

How you address the problem?

Well, like I mentioned, my preference was to switch topologies
to eliminate the critical feature (discharge switch and that if it
is too variable, it causes even more variation in the desired
timing ramp).

The alternative (if this is the problem) would be to work on
the "discharge-done" comparator and squeeze all the timing
variation out of it that you can. But you are probably in some
kind of box, speed / power, and may not be able to go fast
enough to hold PVT timing tolerances using a low power
(hence slow) comparator - switch lineup.

Have you examined the feature / behavior I brought up, and
decided whether this is the cause of your variation? One key
question is, whether the "problem like this" is what I or you
think.

AMSA84 said:

Hi all and thanks for the reply.

In a matter of facts, I managed to design that sawtooth generator. However I found that problem after doing the layout.
What I did was to keep the layout as simple as possible, straighforward connections (without much L curves) and by tunning some components.

The reason I asked that was to ascertain how people do when they cross with a problem like this.

How you address the problem?

Click to expand...

I guess shave off the necessary pF due to layout and input capacitance by geometry and material selection.

Hi guys,

I manage to put the sawtooth working properly. I had to take into account the parasitic capacitance of the RC extraction to design the sawtooth.

However, now I have another problem. When I do the PVT corners, I notice that the sawtooth frequency varies more, for example with temperature maintaining the others fixed. The same goes to the process. Regarding the power supply, the variation is acceptable.

Does anyone know how can I make the circuit more robust to temperature variations?

If the sensitivity of your circuit against layout parasitics ( for instance using very large R and small C ) the effect of layout unwanted components may be very disturbing.It totally depends on layout topology.For instance, in order to obtain a certain R-C time constant, there are tons of possibility to realize this time constant.If you select "the C" very small and very large R value, a small amount of parasitic capacitor value will change too much RC time constant.Or vice versa..
It's just an example and I have faced to face in many times such cases.So, the layout is surely important but design sensitivity is important too..

Thanks for the reply BigBoss.

My circuit doesn't use an RC network. That is, without counting with the resistance of the mosfet that injects current into the capacitor. I am using a current source to charge the capacitor and then a mosfet in parallel to discharge the capacitor.

So you are suggesting that I should use a large C value? Don't forget that I want a very high frequency from the sawtooth.

Regards.

AMSA84 said:

Thanks for the reply BigBoss.

My circuit doesn't use an RC network. That is, without counting with the resistance of the mosfet that injects current into the capacitor. I am using a current source to charge the capacitor and then a mosfet in parallel to discharge the capacitor.

So you are suggesting that I should use a large C value? Don't forget that I want a very high frequency from the sawtooth.

Regards.

Click to expand...

I'm not suggesting to use large or small capacitor value.I have just suggested that the sensitivity against all ( process variations,temperature,layout parasitics etc) disturbing effects of design.If you drive a capacitor by a current pump, how much a small fraction cap. value which is coming from layout parasitics will shift the circuit performance.That's the question..
Regarding to this, you should take the extrinsic effect into account to minimize them..

Ok. I got it. But going back a little bit, regarding the PVT, how can I make the circuit less sensitive to for example temperature effects? And/or process parameters?

Many factors are temperature sensitive, unless you reveal your parameters or design details, how can we tell?

Use temp compensation or a whole different topology like ECL.

What BW to rep rate ratio and F tolerance are shooting for? BW is ~0.35/retrace time?

Capacitance on MOSFETs as I recall is PTC and Vgs(thresh.) is NTC

but biasing comparator at the ideal ZTC ... is that possible for you?
It depends on Vds.

I can reveal, no problem with that. Do you want the topology?

AMSA84 said:

Ok. I got it. But going back a little bit, regarding the PVT, how can I make the circuit less sensitive to for example temperature effects? And/or process parameters?

Click to expand...

Watch this.
https://www.youtube.com/watch?v=hfdZabCVwzc&index=15&list=PLtq84kH8xZ9HIYgBYDsP7TbqBpftidzI8

AMSA84 said:

I can reveal, no problem with that. Do you want the topology?

Click to expand...

No I don't want to analyze your design. I want you analyze and test it and compare with your expectations and show schematic.

What is Vgs?
What is sensitivity of f with Vds?
Does slew rate change on both ramps of sawtooth?
Is it constant amplitude?

AMSA84 said:

So you are suggesting that I should use a large C value? Don't forget that I want a very high frequency from the sawtooth.

Click to expand...

To create a sawtooth wave, there needs to be very rapid discharge of the capacitor. Therefore some component needs to conduct a lot of current. It needs to go to very low ohms, to discharge the capacitor quickly.

Suppose the proportion of the discharge time gets just a little longer (due to limitations of components at faster frequencies). Then your sawtooth wave will develop a little more slant. This will effectively reduce your frequency.

Therefore the smaller your capacitor, the faster it can discharge through a given resistance.

BigBoss, that was a very nice tutorial. The concept is very nice. It is possible to do the same thing in Cadence?

Sunny, as for your questions, for example, when you ask "What is sensitivity of f with Vds?", how can I change the Vds and see the effect of it in the frequency? Vds is not quite a controlled variable, right?

AMSA84 said:

BigBoss, that was a very nice tutorial. The concept is very nice. It is possible to do the same thing in Cadence?

Sunny, as for your questions, for example, when you ask "What is sensitivity of f with Vds?", how can I change the Vds and see the effect of it in the frequency? Vds is not quite a controlled variable, right?

Click to expand...

Yes, sure but the methodolgy of Cadence is a bit different but it will give the same result.