CMOS PVT independent multi-vibrator design.

[imrankhanPNU]

I am doing PVT analysis of an RC-based multi-vibrator. Simulations under varying temperature (0-100 C) and process corners (FF, FS, SF, SS) show signal delay in the modulated signals. This delay is due to the effect of temp and process on R1, C1, and MOSFET's threshold voltage.

-I used PVT independent Schmitt trigger (ST) with fully adjustable threshold voltage to mitigate the modulated signal delay, but the ST does not work in delay mitigation.

Please comment: Is PVT-independent ST a wise choice to mitigate signal delay? How can o get PVT-independent modulated signal?
Note: I implemented the circuit in CMOS 0.35 technology.

Thanks.

 

[frankrose]

Hi,

It is not too wise choice, mainly because ideal ST doesn't exist and steepness of transient signal depend on RC constant.
PVT independent delay doesn't exist, you have too specify an accuracy and there are circuits and technics which can produce maybe what you need.

Btw, if you are using ideal ST (=there is no MOSFET) it makes no sense to simulate FS,SF corners.

 

[imrankhanPNU]

Hi,

It is not too wise choice, mainly because ideal ST doesn't exist and steepness of transient signal depend on RC constant.
PVT independent delay doesn't exist, you have too specify an accuracy and there are circuits and technics which can produce maybe what you need.

Btw, if you are using ideal ST (=there is no MOSFET) it makes no sense to simulate FS,SF corners.

Thanks for your comments. I agree with your suggestion "PVT independent delay does not exist" and modulated signal will exhibit delay due to PVT, Could you suggest some techniques to minimize the delay?

 

[frankrose]

Apply somehow calibration, use quartz instead of RC, use regulated supply (LDO), sense temperature and generate negative feedback.

 

[dick_freebird]

For crude uses like PWM oscillators, I like a switched-resistor
and capacitor with 1/3VDD and 2/3 VDD comparators (ala
NE555). Using a thin film resistor can get you to near zero
T sensitivity and the VDD-referenced divider minimizes V,
leaving you with only P (res make, cap make) variation.
And those, you could trim if you liked.