CMOS Power dissipation

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Ponmalar21

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What is the main reason for CMOS having low power consumption compare to P-MOS and N-MOS?? Is there any fabrication difficulty in that??
 

A purely historical question, nobody makes NMOS (or PMOS) only ICs these days.

The answer should become obvious with a brief review of logic family design principles. NMOS and PMOS are using load resistors which involve permanent quiescent currenr, CMOS doesn't. https://en.wikipedia.org/wiki/Logic_family
 
The complimentary operation is that at any given point of time only one MOS is On.Hence the standing/quiescent current thru the MOS is minimized.This results in reduction of static power disipation
 

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