CMOS Mixer Chopping & Multiplication and NoiseFigure Pro

Dear all,

For the Noise Figure Problem:
In the previous reply in this newsgroup, someone said that the Chopping mixer is lower NF compared with the Multiplication one. However, in the chopping principle, the large signal switching will create larger noise compared with the multiplication. Morevoer, the feed-through effect to the IF. It will make the noise much larger than the multiplication mode.

In the simulation, the chopping is smaller NF than the multiplication. WHY? As I think, the IF power in the chopping mixing is larger than the multiplication mixing. Therefore, SNRout is larger and make the NF lower. Do my this explanation correct?

For the Chopping and Multiplication Problem:
In the chopping, the transistor will switch between cut-off and saturation region. However, as the transistor switch to the saturation region, the impedance will be larger compared with the linear. Then, the output power will lower in the IF. Actually, is the chopping switching between cut-off and LINEAR instead of the cut-off and SATURATION?

On the other hand, could CMOS working as multiplier? I means working as the two sin waves in multiplication. Is it just could work at sub-threshold region only?

I am really your expert helping.

Best Regards,

wccheng

Re: CMOS Mixer Chopping & Multiplication and NoiseFigure

In the multiplication mixers the devices are always on and in triode region, therefore the noise contribution is very high and it entirely couples to IF. Check the attached Steyaert paper on this argument.

nathan

Re: CMOS Mixer Chopping & Multiplication and NoiseFigure

I recent notice that the sampling mixer gives a +6dB NF advantage

**broken link removed**

see also post by search for "tayloe"

That is because all signal energy is transfered to IF instead of beeing split into 2*LO and IF because of the multiplication. The issue with the sampling is switching noise feedtrough into RF and noise of the device. A remark to the analysis found above is that it does not take into account the duty cycle of the switch. That could worse the transfer function because not the peak level is transfered to the cap but some intermediate level depending on the duty cycle.

Dear all,

I have found that the communtating 4 CMOS transistors in the LO part (Gilbert Cell Mixer) are working between cut-off and linear region. Since the loading is resistor or active load, it could not be in saturation mode. As the loading is the inductor, they could work between cut-off and saturation region. However, it is not possible to use the on-chip inductor as loading because the frequency is usually very low (IF). I think the inductor loading is possible in the high IF. Am I right?

Best Regards,

wccheng

Dear all,

For the CMOS, is it not possible to work it as multiplication under ordinary condition?

As I saw the book said that the CMOS could work as multiplication in the sub-threshold voltage bias.

The 2nd method, is using the non-linear of the CMOS transistor in order to get the multiplication.

Are these correct?

Best Regards,

wccheng

Re: CMOS Mixer Chopping & Multiplication and NoiseFigure

Pure multiplication have some advantage if you do not want to convert the third harmonic. But for downconversion rectangular multiplication function is wanted because you get 2/Pi instead of 1/2 for current mixing. Also there is less sensitivity against LO amplitude variation. That is because bipolar and mos try to switch hard. For bipolar you need about 200mV, for mos 500mV-1500mV.

Dear rfsystem,

I am very thankful for your reply. I know this is the different between the multiplication and the mixer. ( very thanks for other people reply my problem before ).

If I really need to use CMOS to do the multiplication, is just to use (1) the non-linear effect of the CMOS and (2) sub-threshold bias in order to do the multiplication?

Sure, the paper suggested by Mr. Nathan is another method to do the multipliaction using CMOS.

Best Regards,

wccheng