CMOS LDO with utr-low ground current

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billchen

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what is ldo ground current

I am designing a utr-low quiescent current CMOS LDO.
To meet spec,the current source of OP(single stage) is only 0.4uA.
When load current is 1mA,the parameters of regulator loop sre as following:
P1:8Hz @Vout of OP
P2:2KHz @Vout of LDO,load capacitor is 1uF,Resr=10m
UGF:4KHz
Phase Margin:22
Use compensation capacitor at the Vout of LDO,i can get a zero at about 10K, and it will be useful when the load current is upper 10mA.

The line & load transient are both very poor,what can i do to improve them,pls pride your great idea.
The main reason of poor line and load transient is long response time, is it right or not?
If improve the loop gain and increase the UGF,then the ac stability will degenerate. How to trade off them?

Thanks

If you need more informations, pls tell me.
 

ground current for ldo

You can insert a capacitor across the output of the LDO and the feedback pin of your error-amplifier. This configuration creates a zero and a pole. By using suitbale RC value, the zero can be used to increase the loop-bandwidth, improving the transient response.

Hope it helps
Scottie
 

low ground current amplifier

Thanks for your help.
I have added the capacitor to improve the ac stability.But when the load is smaller than 10mA,the zero get from the capacitor is upper than UGF,so is is unuseful.
It will be a little help when load current is bigger than 10mA.

Can anyone give me more respons.
Thanks
 

ldo ugf



1.The P.M is so small ,your LDO will become a oscillator in some application.
2.B.W (UGF) is too small,the line transient response and load transient response is not so good.
3.Yes ,You can improve line/load transient response by improve UGF .
4.You must re-assign the pole and zero allocation of LDO
5.how much loop gain do you have ?
 

You can consider using the ESR of the output capacitor, which can forms a extra zero for you. Of course, larger the ESR, larger the spike during line/load transient.

My suggestion is, unless you change your topology of your LDO, it is very difficult to achieve what you want.

Scottie
 

Thanks firstly.

to tsanlee
The loop gain is about 64dB @1mA load current.

In the topology,there are 3poles and 2 zeros.
P1 @ Vout of OP,a little change when load current changes,because of the Miller coefficient's change. (from 5Hz to 50Hz)
P2 @Vout of LDO, change quickly with the load current.
Z1 &P3 are all get from compensation capacitor,Z1 is a little smaller than P3,when the load current is more than mA magnitude,it will be a little help to AC stability.
Z2 @ Resr,greater than UGF because the value of Resr equals 10m in the simulation.

The worst-case stability condition occurs when the load current equals 10uA and Rear=10m and.The Phase margin is only 14.

It's impossible to change P2.It's difficlut to change P1.
Z1 and P3 are at the suitalely position.


to scottieman
I have considered the ESRof output capacitor.But because the UGF is small,so when the Resr=10m ,the zero is upper than UGF,it;s useless.



What can i do to improve line and load transient?
 

Mind to let me know what kind of technology you are using (CMOS or BJT)?
What is the technology node you are using (e.g. 0.6um or??).

Scottie
 

Re: Thanks firstly.


1.The DC gain is OK

2.The P1 is too low, i think the impedance of erroramp is to large or your Cgs of driving PMOS is too large.
--> Can you reduce the ro of erroramp ,or reduce the PMOS (can reduce the Cgs ,but you must take care the dropout voltage or drive capability )

3. the DC gain of driving PMOS in light load is more than it in heavy load.
--> Gpmos=gm(Ro||ro)=√(4KID) Ro=√(4KVout/Ro) *Ro=√(4kVoRo)
Gpmos≈K√Ro
When it in ligh load,the LDO have poor GM.
4.My suggestion is 'Re-assign pole and zero of LDO "
-->in normal application, the ESR is only under 1~2 Ohm
You can not let this zero in low frequency.
 

to scottieman
1.5um CMOS technology


to tsanlee
Thanks for your detailed reply.

2.The P1 is too low, i think the impedance of erroramp is to large or your Cgs of driving PMOS is too large.
--> Can you reduce the ro of erroramp ,or reduce the PMOS (can reduce the Cgs ,but you must take care the dropout voltage or drive capability )

--------Increase ro of erroramp,the DC gain vill decrease.How to trade off?


4.My suggestion is 'Re-assign pole and zero of LDO "
-->in normal application, the ESR is only under 1~2 Ohm
You can not let this zero in low frequency.

--------Because the BW is about 5kHz, Even the Resr=1,the zero get from it is at 160kHz,unuseless.
 

you may consider adding a buffer between the output of error amplifier and the gate terminal of the PMOS power transistor.

Scottie
 

scottieman said:
you may consider adding a buffer between the output of error amplifier and the gate terminal of the PMOS power transistor.

Scottie
Click to expand...

The buffer will consume quiescent current, and it will make circuit complex.

Thanks to you and tsanlee.

I just have change current source of erroramp from 0.4uA to 0.8uAto inprove line and load transient to meet spec.
 

Good News, you slove this problem.

In the low quiescent current circuit.you must take care the device leakage.
The bias current in any device is very weak, so the effect of leakage current is important.
 

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