-- Posted this in the job section, nobody seems to be replying --
Hi All,
Could anybody tell me what kind of questions are generally asked from Digital CMOS layout during a job interview ? I have an upcoming interview coming up for design engineer and there is a dedicated session on layout.
I suppose you might have to concentrate on DRC rules such as spacing between metal layers, Antenna violations, Electro-migration , usage of vias--single and multi cut..,
Classic questions on Inverter characteristics, Secondary effects of MOSFET will be always there
pavan is right. You should concentrate on DRC rules based question. Few of the Basic question which I usually ask during interview is mention in the following blog. Have a look on these question. These Questions are very easy but sometime we mis to prepare these. VLSI Questions: DRM Related VLSI interview questions
Wow. This is great stuff. Thank you so much birdy and pavan. I am currently going through the book IC Mask Design by Chris and Judy Saint, but in no time, I am going to look into those questions and I am quite sure I have to get back here regarding answers to some of them.
(Actually, it would be great if you could post the answers too, that would save us from digging through books and internet - although I do agree that digging makes us learn more )
Sure I will try to compose the Answer of these questions and let you know ASAP. But still I will suggest to use your experience of answering these questions. because the few of them are very tricky (tricky in the sense .. if you have worked over these then its very easy to understand ), but still I will try my best.