CMOS invertor pushpull amplifier: how to reduce output impedance

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mvs2011

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Hi, I am using an invertor based (pmos on top and nmos at the bottom) output stage. I cant use the one with nmos on top and pmos at the bottom as it requires a wider input range for the output range needed. Now, the invertor based output stage has very high output impedance and is causing stability issues. Wonderign if there is a way to reduce it.
Thank you!!
 

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Thank you for the suggestion. I was wandering if there are any topologies that could be used for this purpose, something like a super source follower sort of. I tried connected a diode connected pmos between supply and output of the invertor and having a fixed current source between supply and gate/drain of this pmos to define its bias current - since a diode connected devcie has output impedance of ~1/gm, i am expecting the overall output impedance of the invertor to come down but that did not improve things much..trying to do something on these lines..
 
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mvs2011 said:
I tried connected a diode connected pmos between supply and output of the invertor
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I would have said that it is equivalent to connecting a load to the inverter's output itself but not modifying the output impedance of the inverter stage.
If I were you I would have tried the topology seen below:

This is exactly what you want to achieve (as far as I understood). The output can swing very close to the rails, if the input from the previous stage has increased, the output inverter-based stage will push/pull current into the load while keeping the gates of the devices( their CM) constant ish. That ensures that the output can swing close to the rail before transistors in the output stage enter triode (especially the active one).
Of coarse you have to make devices in the output stage wider to drive a really heavy load (low-impedance one).
 

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D.A.(Tony)Stewart said:
Define Zo, or gm, or RdsOn, Vdd , BW, Pout, etc then I can suggest Vt and Beta values
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Thank you, i dont have these yet, basically trying to see what variants of topologes are available..
--- Updated ---

Thank you, this would still be an invertor i.e. have higher outptu impedance than a source follower. So, I am not sure if this would work for me.
 

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THis output stage along with gain stage will be part of feedback amplifier, feedback used for fix gain and the output impedance is usually rout/(1+AB) wehre B is the feedback factor. Are you refering to this feedback taht eventually reduces the output impedance i.e. the output impedance of the invertor? Thank you!!
or are you refering to any feedback mechanism just for the invertor, in which case can you please site an example to refer to. Thank you!!
 

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It's not much without lots of loop gain.

It is better to start with good specs. Is this for logic or analog? Vdd((min) ? Rout max?

Rout = (ro∣∣RD)/ (1+Aβ)
where Aβ is the loop gain.

Logic does not use feedback ie. "CMOS Inverters"
 

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It is for an analog output. I dont have the complete specs yets but I am sure the output impedance of the driver stage (invertor) is going to have high enough output impedance and that would create issues in stabilizing (since it will be a pole at lower freq. thought it is not the dominant pole) the amplifier (gain stage + invertor output stage). So, trying to see what options i have in terms of lowering the output impedance of this invertor to move the pole to a higher freq. I could use miller compensation but that would move the dominat pole to lower freq. which i am trying to avoid because of bw requirements.
 

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