CMOS Inverter gain/phase calculations.

[transcendent]

Mostly a continuation from my problems from yesterday. I've tried without much success and need some further help with analogue theory/hand calculations.

Circuit in question is the CMOS inverter hooked up to work as an amplifier.
**broken link removed**

Here is the small signal simulation:
**broken link removed**

The max gain comes out as 152 from simulation. (1.52 on the graph / 0.01V AC)
I did a standard calculation of Id through the PMOS from:
Id = beta(vgs-Vt)^2 = 2.744e-6
gm = 2 x sqrt(beta*Id) = 1.6632e-5
go = lambda*Id = 5.488e-8
A (for the pmos) = GmRo = 303.

This is about double the actual gain. How does the nmos and pmos mathematically come to the correct theoretical gain? This *Should* be simple, I'm just not very good at this.

Secondly, how is phase -frequency response calculated theoretically. This I have even less of a clue about. And I can't think why on the graph the phase changes from -180 to +180 in the middle of the bandwidth. Full explanations in a user listen friendly format would be much appreciated.
Thanks in advance.

 

[leo_o2]

I worried about your calculation. It is only suitable for satuation region. As a inverter, MOS might not be in satuation region.

 

[transcendent]

Well, Vgs is biased to be higher than Vth, in all cases. And Vds maybe should be higher than Vgs - Vt when it's pulled to the maximum of one direction?

I'm thinking maybe just the output conductances add-lowering the overall output resistance at Vout. Since the FET's have been approximately matched, this would equate to half the output resistance of one FET. Thus giving the required gain of 151.5? hmm

Does no one have any thoughts about solution/any of the other observations?

 

[sina_extreme]

i think I'd go with the output conductance you just mentioned
since both TRs are matched so it wouldn't differ which one is conducting
so maybe reconsider the output resistance