Cmos inverter Design (Issue -output spike)

[Anand15]

Hi all,

I am designing a inverter in 0.25u tsmc tecnology.
when i am doing transient simulating i am gatting spike.
VDD=2.5V. spike around 0.1v.
even the DC characteristic is perfect.

Thanks & Regards
Anand

 

[ankitgarg0312]

is this spike coming at trasition time
can you post picture of waveform zooming region of spike??

 

[Anand15]

I am sending transient waveforms

 

[ankitgarg0312]

sorry i can't see any data here

 

[Anand15]

Dear i am unable do atteched any file file or pics.
what I'll do.

 

[ankitgarg0312]

are u not getting the way to upload pic/file or any different issue??

 

[Anand15]

option is there but error is coming...

 

[ankitgarg0312]

as a trial put some cap on output node and resimulate...
if spike decreases then its control system theory of under/over/crirital damping

 

[Anand15]

Ok I'll try..