CMOS inductor with different substrate resistivity

cmos inductor

hello, everyone.

now i have a EM-simulation question about CMOS inductor with different substrate resistivity

the inductor layouts (N=4.5, W=10um, S=2um and Rin=60um) and process parameters are same and the substrate resistivity is 1000, 100, 10, 1, 0.1 respectively, the unit is Ohm.cm.

the theory is that if the substrate resistivity is lower, the Q-factor of inductor is lower due to the more severe influences of lower substrate resistivity.

but from EM-simulation results, the situation is different.
the EM-simulatior is momentum, and the configration is verified with measured inductors.

Q1,3,5,7,9 is the one-port Q-factor of inductor with different substrate resistivity (1000, 100, 10, 1, 0.1) respectively, as shown in figure.

as for Q1,Q3,Q5, the Q-factor is lower and is coherent with the theory.
But as for Q7 and Q9, the substrate resistivity is more lower, the Q-factor is higher reversely.

so, anyone can help me to explain the reason or find any wrong?
thanks a lot.

how to different inductor

When you look the self resonance frequencies of the inductors, No1,3,5 they are all same but No;7,9 much lower than others.So, inductor values are not same anymore.
Zero crossings are at the same time self resonance frequencies.
I guess, because of eddy current ( i suppose the the coil is not shielded by hatched Polysilicon layer ) inductor values become different..
It's my interpretation..