CMOS IC working in a wide supply voltage

Still plenty of 5V technologies in production, much easier to use a
naturally capable process (if you can get the performance - and if
you're setting the goals, with a mature process, that should be no
prob.

You can protect the front end and stack the back end especially on
SOI (or triple well). Tall stacks in basic JI suffer from NMOS body
effect and cascoding cannot help the Vdb limit (which may be more
than Vds, Vdg reliability based limits, but often goes unquantified).

What sets the technology choice? Not like 0.35u is a superstar in
any aspect.

dick_freebird said:

Still plenty of 5V technologies in production, much easier to use a
naturally capable process (if you can get the performance - and if
you're setting the goals, with a mature process, that should be no
prob.

You can protect the front end and stack the back end especially on
SOI (or triple well). Tall stacks in basic JI suffer from NMOS body
effect and cascoding cannot help the Vdb limit (which may be more
than Vds, Vdg reliability based limits, but often goes unquantified).

What sets the technology choice? Not like 0.35u is a superstar in
any aspect.

Click to expand...

Thanks freebird,

As I understood from you that industry use the 5 V still, but how this technology accept a voltage of 1.6 V for example.

Generally can I use smaller voltage than recommended by technology?, like in my case with 0.35 µm, can I propose design with 1.8 V on this technology?

Almost every process is providing so-called I/O devices, which are mosfets using thicker oxide. Usually, 0.35um process provides I/O devices with nominal 5V.
And yes, you can use lower supply as long as your circuit is operating. Academia is fighting with Circuits operating down to 0.3V. Industry has to deal with supply between USB (5V) and battery (1.5V).

Dominik Przyborowski said:

Almost every process is providing so-called I/O devices, which are mosfets using thicker oxide. Usually, 0.35um process provides I/O devices with nominal 5V.
And yes, you can use lower supply as long as your circuit is operating. Academia is fighting with Circuits operating down to 0.3V. Industry has to deal with supply between USB (5V) and battery (1.5V).

Click to expand...

Thanks Dominik,

You mean to say that I/O devices use higher voltage, but what about the internal circuits?

You want a circuit that works from 5.5V all the way down to 1.6V and you are facing headroom issues since the 5V devices you used have too large a Vth to operate properly at 1.6V supply.

Process selection is the start. You want a cheap process that has the devices you want. For example TSMC 0.18um process has flavours with 3.3V I/O devices or 5V I/O devices. And this is usually the case with most process nodes, the I/O devices have multiple flavours.

A "simple" solution to the voltage range problem could be to use a simple charge-pump / voltage doubler which gets enabled once the supply is less than say 2.5V. This can provide a higher supply rail when the actual supply is too low. No extra masks or anything but extra circuitry.
Or you can use some specialty devices such as low Vt devices and what not. But this is at the cost of extra masks.
Or you could use some of those low voltage supply circuits and see if those can be modified to operate over the larger range.


Also, for standalone analog parts such as opamps or comparators, there aren't usually any "internal" circuits or any digital which would require an LDO or anything. If any digital is still present, it could just use the I/O devices and operate at a much lower frequency to deal with the timing.

You can use "I/O" devices in the "core". You may see some rules imposed
(like latchup rings) if the DRC is unsophisticated, that hurts only area.

The difference in VT between 0.6u ("5V" lowest L I've seen, and best pad
it a little for analog) and 0.35u is probably 100mV or so. Not the killer.
You'd just be a bit deeper into subthreshold but that's where you want
to be anyway, for DC qualities. Speed, you'll suffer.

There are "over the rail" op amps which employ charge pumps (and
noise mitigation tricks).

Junus2012 said:

You mean to say that I/O devices use higher voltage, but what about the internal circuits?

Click to expand...

Everything depends on your needs.
Level shifters, multiple domains, LDOs are used for some purposes.

Dear friends,

Thank you very much for your answers and nice explanation you provided me.

Yes the 0.35 µm technology I am using it supports the 5 V I/O,

But the core module is still 3.3 V, so do you mean that 5 V I/O pads will clamp the 5 V to 3.3 V ?,

Thank you

"Library pads" might have in-built ESD circuitry (just diodes, or more)
but there should be 5V pad family if there's 5V devices. I/O libraries may
be separate from core. Doing the right thing for supplies is key.

I think there is some misunderstanding here...

In your original question, you mention having to use 2.8V to 3.6V supply. Is this range coming from the system specifications or from the process selection or from the design?

Also what do you mean by "core module"?

Thank you once again, friends,

I am near to understand it but not completely,

The technology I am using support both 3.3V and 5V CMOS main modules.

As you also mentioned before, I can use the 5V modules and supply the circuit with 3.3V taking in to consideration the threshold voltage of the 5V module.

However, I am actually using the 3.3 V CMOS module. When I go to the data sheet, I read the maximum voltage I can use is 3.6 V. That is the origin of my question, I see the available voltage range is very tight to the nominal value as compared to the industrial chips where always they show a wide range of supply compatibility.

Then most of you my friends emphasized on the solution of the I/O pads, which means I can use 5V I/O pads to support my 3.3V MOS, in this case, the pads will be powered by separate supply rings from the core module,

I have my conclusion is correct,

I am really thankful to your contributions and help

Regards

"Process module" refers to some group of steps that define feature(s).
Like the "core" thinox is one and the I/O (which might have 3.3 and 5V
options, but you only get one) another.

The totality of the built device set is what you get to use and live with.

Wide operating range is had by device reliable BVdss and circuit tricks
(whichever may be practical in the flow and application) and the low end,
by MOS reliable subthreshold operating range (pinned between VT
and the worst case leakage floor). More art and compromises are
necessary as the ratio of Vout (BVdss / HCE limits) to Vin (VT /
intersection of subSlope and leakage floor) reduces. Like, a 40V MOS
with a 2V VT has a "range" of 20:1 while your core finFET with its
0.9V drain rating and a 0.4V VT is a hair over 2:1 (and op amps I've
seen made, according to traditional topologies scaled, suck-suck-suck).

Design is all about goals/specs/expectations then analyze the tradeoffs and make choices.

You know that short circuit current is a function of Vdd/ RdsOn and slew rate is also a function of RdsOn at the std test of 30 pF. When designs require lower Vdd they need a lower Vt to achieve 100, 50 or 25 ohm standard nominal RdsOn values for logic and analog can be anything in between or beyond. But with a lower RdsOn you also get a higher Coss which impacts on the GBW and slew rates.

So my point is what are you hoping to achieve assuming both 3.6 or 5.5V technology are possible.

e.g. the SMP5496 is about 100 ohms for Nch at 5.5V and slightly higher 116 ohms at Vdd=1.6V
It also has Aol = 105 dB min and 30 MHz GBW.,

It is not ok just to make anything using 0.35 um.

Your MCP6549 open drain comparator performs better at low Vdd mainly due to the lower swing voltage at low currents even though RdsOn is much higher at Vdd=1.6 but the toggle frequency is higher and that is better.


So what do you hope to achieve? List the target specs.

I'm sure Dick can help you with the tradeoffs, he's an expert on these designs.

Thank you very much friends for your answers, it was really helpful to understand this issue