CMOS dopinf of substrate and nwell

CMOS doping of substrate and nwell

Would a NMOS work if the substrat ist p+ dopted and the nwell of the pmos n+?
What's the reason it's n- (ie less dopted than the contacts)?

Re: CMOS doping of substrate and nwell

yannik33 said:

Would a NMOS work if the substrat ist p+ dopted and the nwell of the pmos n+?

Click to expand...

May be, but it's not done, because you would have to over-dope the transistor areas. However around these transistor areas you can have highly doped regions (p+ in substrate, respective n+ in n-well). As dick_freebird noted, many flows allow for direct contact between p+ and n+ regions.

yannik33 said:

What's the reason it's n- (ie less dopted than the contacts)?

Click to expand...

You think of n- doping of the n-well (or p- of p-substrate)? One reason is that you don't have to over-dope the transistor regions (s. above). Another reason is that you get sufficiently high series resistances in order to keep Beta of the parasitic BJTs low enough to avoid latchup.

I have designed products in a Nsub, Pwell technology. It
was the only one of maybe 20 CMOS flows and subflows
in our process portfolio (at the time) that was this way.

Construction of this sort gives you a NPN vertical BJT
parasitic about the NMOS, rather than a PNP parasitic
about the PMOS. Tends to be higher gain (esp. if you
do not make the Pwell retrograde, and this is not so
easy because boron likes to diffuse) and so worse for
latchup.

But at the time it was one of the faster 1.25um CMOS
processes out there (0.8um was a technology development
stretch) and the most radiation-hard commercial CMOS
in existence. One good thing about a N- field is that you
don't need field implants to control leakage from various
trapped-hole actors. The Pwell, you can tune and will
shoot it anyway. Psub processes need field implants
(at least at the lighter doped, higher voltage nodes -
I know nothing much about deep submicron but do
know that as low as the 0.18 I work in now, field implant
still needs a mask and several process steps).