cmos as simple switch

mona123 · Mar 2, 2015

Hi, I want to use cmos as a simple switch. What gate length should I choose, minimum or anything larger than minimum? Thanks.

nitishn5 · Mar 3, 2015

Hi mona123,

Since you would want to have the minimum resistance in a switch, you should be going for a minimum length design.

Find out how much resistance you can handle, and run some simulations to find the resistance of a switch across all input voltages. And select the length where the resistance matches your requirements.

kenambo · Mar 3, 2015

It is also be chosen by your switching current requirements that is also related to the resistance you handle.

mona123 · Mar 3, 2015

Thanks. If I can handle larger resistance, any advantage of going larger gate length?

nitishn5 · Mar 3, 2015

The CMOS Switch even when OFF, will have some leakage. This will be worse with smaller lengths.

The amount of leakage is quite small in the order of pA to nA depending on the width and increases with temperature.

But if you are dealing with super high impedance nodes which cannot support any current, then it could be a problem. So you will need to have a larger length.

I have faced this so i know!

mona123 · Mar 3, 2015

Thanks nitishn. Is it possible to explain a little bit more. I think that's the information I am looking for.

nitishn5 said:
The CMOS Switch even when OFF, will have some leakage. This will be worse with smaller lengths.

The amount of leakage is quite small in the order of pA to nA depending on the width and increases with temperature.

But if you are dealing with super high impedance nodes which cannot support any current, then it could be a problem. So you will need to have a larger length.

I have faced this so i know!

nitishn5 · Mar 3, 2015

Hi mona123,

Let's assume that your switch is between a high impedance node (lets call it 'Node_h') and some other node (Node_o).
For example some low power bandgap and an Op-Amp input gate.

Now let's also assume that the Node_h cannot support ANY current, even to the order of pA.
Now without the switch, the Node_h is connected directly to Node_o which is a gate and hence there is no current drawn.

But when there is a switch between the two nodes, Node_h sees a source/drain of the switch which can leak even if the switch is turned OFF.

Normally this leakage would be quite small. But at high temperature and for large Width of the switch, the leakage can get quite large.
And this will start to load your high impedance node Node_h. And if Node_h cannot handle it, it will be screwed.

In order to reduce the leakage, you can increase the length.
The advantage here is that since you are only transmitting a voltage and not a current, you do not care about the resistance of the switch so it could be higher.

mona123 · Mar 3, 2015

Hi nitishn5, Thanks for explaining. I am still wondering, what can go wrong from you statement "And if Node_h cannot handle it, it will be screwed". I have similar scenario. Can you please explain. Thanks for patience.

nitishn5 said:
Hi mona123,

Let's assume that your switch is between a high impedance node (lets call it 'Node_h') and some other node (Node_o).
For example some low power bandgap and an Op-Amp input gate.

Now let's also assume that the Node_h cannot support ANY current, even to the order of pA.
Now without the switch, the Node_h is connected directly to Node_o which is a gate and hence there is no current drawn.

But when there is a switch between the two nodes, Node_h sees a source/drain of the switch which can leak even if the switch is turned OFF.

Normally this leakage would be quite small. But at high temperature and for large Width of the switch, the leakage can get quite large.
And this will start to load your high impedance node Node_h. And if Node_h cannot handle it, it will be screwed.

In order to reduce the leakage, you can increase the length.
The advantage here is that since you are only transmitting a voltage and not a current, you do not care about the resistance of the switch so it could be higher.

kenambo · Mar 4, 2015

Hi ,

As you said, If we connect a switch in your example, There is no ground path for the switch to leak the current. Since the other node is connected to the gate unless there is no bulk current flow. Am i right?

Can you please explain this?

nitishn5 · Mar 4, 2015

mona123 said:
Hi nitishn5, Thanks for explaining. I am still wondering, what can go wrong from you statement "And if Node_h cannot handle it, it will be screwed". I have similar scenario. Can you please explain. Thanks for patience.

I have attached an Image.

Here the High Impedance Node, Node_H has an impedance of 10GOhms.

If input is say 2V, a leakage of just 10pA means a voltage drop of 1V at Node_H...!

Now even if the Other Block does not draw any current, the switch will take some leakage current whether it is ON or OFF.

While the switch is OFF, it might not be a problem(I'm not sure, It depends on your design).
But while the switch is ON, you want the Node_A = Node_H = 2V.
But if there is some leakage, this will not happen as there will be a voltage drop.

There is a paper on Leakage Mechanisms in MOS by Kaushik Roy.

kenambo · Mar 4, 2015

But the above explained thing is true for Ground referenced circuits and It wont happen for the circuits which do not reference ground like gate connection.

And by using it as a switch, we don't have such a high impedence on top of the switch. Since switch is for allowing the voltage what is getting on top of it.

mona123 · Mar 4, 2015

Thanks for the discussion. I'll try to think more.

nitishn5 · Mar 4, 2015

I forgot to attach the image...!!

erikl · Mar 4, 2015

nitishn5 said:
https://obrazki.elektroda.pl/5095799300_1425449075_thumb.jpg

In this case you should not connect source to bulk, as the NMOS bulk usually is substrate=GND (if you don't use a double/triple well process or SOI substrate).

nitishn5 · Mar 5, 2015

erikl said:
In this case you should not connect source to bulk, as the NMOS bulk usually is substrate=GND (if you don't use a double/triple well process or SOI substrate).

But that would mean extra masks and extra cost...!
Not worth doing just for singular instances like this.

erikl · Mar 5, 2015

erikl said:
... use a double/triple well process or SOI substrate

nitishn5 said:
But that would mean extra masks and extra cost...!
Not worth doing just for singular instances like this.

Of course not worth. That's why I said one shouldn't connect source to bulk (as shown in your image), because this would short circuit the input to GND.

nitishn5 · Mar 5, 2015

Oh yeah...!!

I had Double N-Well available in my case from where I lifted this image.

Anyway, I had some other reasons for doing that. I am using it just as an illustrative example of what can go wrong even with what looks like a simple situation like this.

cmos as simple switch

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