Eng.islammostafakamal
Newbie level 2
I'd ask about the CML Divider as i design for 2by3 Cell at the first two stages in the divider chain as
it should operate with high frequencies
First stage should divides from 3.5G --> 2.4G
second stage should divide from 1.75G --> 800M
My problem is that the first stage can't cover the whole range of frequencies. it operates well till 3G only
the same problem with stage two too.
how could i extend the transient frequency range ?
Note: i have tried to increase delay of the last latch to support low frequencies but i have found that 3G is the edge of proper operation.
thanks in advance
it should operate with high frequencies
First stage should divides from 3.5G --> 2.4G
second stage should divide from 1.75G --> 800M
My problem is that the first stage can't cover the whole range of frequencies. it operates well till 3G only
the same problem with stage two too.
how could i extend the transient frequency range ?
Note: i have tried to increase delay of the last latch to support low frequencies but i have found that 3G is the edge of proper operation.
thanks in advance