Oct 20, 2009 #1 T tiportoolmo Junior Member level 2 Joined Sep 10, 2009 Messages 20 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,426 CML comparator Hello everyone. I need to design this circuit for a full flash ADC 4 GS/s in 65nm CMOS. There are some rules to do that? for example, how can I choose W, I bias and Rload for this circuit? please, I need a big help. circuit:
CML comparator Hello everyone. I need to design this circuit for a full flash ADC 4 GS/s in 65nm CMOS. There are some rules to do that? for example, how can I choose W, I bias and Rload for this circuit? please, I need a big help. circuit: