CMFB loop stability problem

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pseudockb

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CMFB loop stability

Hi, I am currently designing a fully differential folded cascode OTA with difference differential amplifier CMFB network. My CMFB network does not seem to be working as it should. After some reading, to my understanding is that the CMFB loop should be stable in order for the negative feedback to kick in. My question is, how do we usually simulate the frequency response of such loop?

Another question I would like to ask it that: What is the function of the testbench in pg 35 of the following document?
**broken link removed**
Thanks for the help.
 

Re: CMFB loop stability

In the page 35, Vcm give the common mode voltage input, L is to isolate the input to the OTA output node. Actually, it is test CMFB transfer function
 
Re: CMFB loop stability

if u are using spectre try the stability analysis
 

Re: CMFB loop stability

I'm not using spectre. I still have some doubts. First, won't the inductors that are included in the testbench of the above circuit affect the frequency response of the loop? Second, if the CMFB loop is unstable, then the output common mode voltage will not be as what is expected. Some of the transistors will not be in saturation region. Is it accurate to simulate the frequency response of such CMFB loop if the transistors are not even biased correctly? Thanks
 

Re: CMFB loop stability

Yes, you are right. The inductors actually affect the CMFB loop transfer function. I tried put the test signal on the reference side, but still seems not correct. Anyone has experence to do the CMFB transfer function simulation?
 

Re: CMFB loop stability

I also want to know how to define de loop gain and loop phase of the CMFB and VFMB loop.In LDO loop,It's easy to do AC simulation to see the loop gain and pahse margin;but when the system becoms to switch mode ,how can we do?need to simulate the control to output delay?
 

Re: CMFB loop stability

1. the LC network is used to break the loop such that AC signal will not pass, so it's value should be large enough (i.e. an LPF with low cutoff freq.) , usually L=10Henry, C=10Farad
2. no, if transistors are not biased correctly, it get the incorrect response.
 

Re: CMFB loop stability

Thanks for your reply. But I am still not clear. Let me rephrase my question. First, I have determined the transistor sizing based on the desired output common mode voltage (VOCM). However, after running simulation, VOCM is not near to the expected value. Its value is near to either supply voltage. The value is the same when I remove the CMFB loop. Thus, I concluded that my CMFB loop is not working at all. Here comes the question. What is causing this CMFB loop not to be working? Is it solely due to wrong biasing condition or is it due to the instability of the CMFB loop?
 

Re: CMFB loop stability

what kind of simulation u had ran? transient or AC ?
u should always run open-loop AC analysis first, after this sim, u will know whether ur OP or CMFB is biased at the correct points or not. u will find DC gain, UGB, PM.
then u can do closed loop analysis which is transient analysis.
Only closed loop has stability problem.
 

Re: CMFB loop stability

I only ran a open loop AC analysis before.So if I understand you correctly, the reason that my VOCM is not at the desired value is due to wrong DC biasing condition, rather than instability of the CMFB loop?
 

Re: CMFB loop stability

yes!
if possible, u can post the result of ur AC response, and its testbench, and we can check it carefully.
 

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    pseudockb

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Re: CMFB loop stability

Thanks for your help. I will try to get my DC bias correct first.
 

Re: CMFB loop stability

So let me get it correct, the stability of CMFB is determined by open loop. This simulation can be done using the testbench on pg.35. In order for CMFB to not affect the settling time of main amplifier its unity gain frequency should be greater than that of the amplifier. Is the unity gain frequency of CMFB measured from the open loop using the testbench on pg. 35?

Thanks
 

CMFB loop stability

Where can I find information in fully differential amplifiers with switched capacitors. I have a circuit that I need to analize (adc converter) and I dont know very well how the voltages behaves before and after the charge transfer.
 

Re: CMFB loop stability

One mistake happens to the test configuration in page.35. The input signal
should be a differential mode test. So, once we do the common mode test
we should give a common mode input signal, right?
 

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