CMFB for opamps & transconductors

[prabhu_psg]

I am designing a 2-stage opamp .A folded cascode gain stage followed by CS stage

I have following problems
1.The output for zero input goes to either Vdd or Vss even if there is change in the bias current by 25uA.Even a small variation in the width of the output nmos of the CS amplifier. If we adjust for zero output the gain of the CS amplifier is reduced. Will aCMFB circuit solve this problem

Please help me

Prabhu.G

 

[philipwang]

You know that only differential input and differential output amp needs CMFB, maybe you can describe your problem more clearly.

I am designing a 2-stage opamp .A folded cascode gain stage followed by CS stage

I have following problems
1.The output for zero input goes to either Vdd or Vss even if there is change in the bias current by 25uA.Even a small variation in the width of the output nmos of the CS amplifier. If we adjust for zero output the gain of the CS amplifier is reduced. Will aCMFB circuit solve this problem

Please help me

Prabhu.G

 

[sutapanaki]

If your design is single ended then no, a CMFB will not solve the problem. If it is fully diffeential a part of the design is in fact the CMFB. If you have a single ended design but you want to simulate the amplifier open loop, then you may have that problem especially for high gains. It comes mainly from the mismatch of the current sourcing and sinking capabilities of the output stage transistors. In normal operation, when you put a feedback around the amp, it will take care to put the output somewhere between Vdd and Vss. But you'll have some systematic input referred offset. You should design initially for low systematic offset.

 

[prabhu_psg]

Thanks for your guidance.
Which output stage will give less systematic offset voltage and can drive resistive loads(DAC's) ?
Pleaseguide me


Thanks

Prabhu

 

[sutapanaki]

The key to small systematic offset is that the current sourced is equal to the current sunk i.e. if you have a resistor as a load there is no current in it i.e. 0 output voltage. So, for zero input you get zero output. This is of course valid also for any other kind of load and we are talking DC.
As a simple example if the first stage is a diff amplifier with current mirror as a load (the standard configuration) - let's say PMOS load, then you usually have a common source as a second stage - PMOS driving transistor and NMOS current source. In this case the PMOST of the second stage should be matched to the PMOS transistors of the load of the diff stage as per their current ratio. The NMOS current source of the second stage should be sized accordingly and matched to the tail current source of the diff stage. This is done to match the current from the PMOST to the current in the NMOST and thus the output is in the middle between the rails. Of course it will not be in reality because of random mismatches, but at least you take care of the systematic offset.
This stage is not usually enough to drive resistive load. One way would be to use source followers as output stage. Or use common source push-pull stages. It is a big topic and you better look in the books and papers for that.