CMFB circuit in Comparator

[chanchg]

Hello

I have to design a very high-speed fully-differential output comparator. If my design strategy is to use 2-stage open-loop millter OTA, then do I have to use some kind of Common-mode Feedback Circuit for this type of comparator. I can design a track-latch comparator(which doesn't need above complexity) but my question is very specific to 2-stage open loop type.

Regards

 

[analogic1]

you need CMFB for your comparator, which is really a fully differential amplifier

 

[nxing]

for any differential in/out amp, you should consider CMFB

 

[Alles Gute]

In high gain fully-differential, output CM level is quite sensitive to device mismatches. To stabilize the output CM level, CMFB is needed

 

[ezt]

I'm not very good in comparator design but I agree with the others. In fully differential applications you should use a CMFB to set the CM level of your output. you can find good and easy ideas in the book by Behzad Razavi ,"Design of Analog CMOS Integrated Circuits", or such a book by Ken Martin and Johns. afterall almost in every paper you can find a CMFB circuit. because nowadays everybody use fully diff circuits.

Regards.
EZT

 

[Btrend]

Hello

I have to design a very high-speed fully-differential output comparator. If my design strategy is to use 2-stage open-loop millter OTA, then do I have to use some kind of Common-mode Feedback Circuit for this type of comparator. I can design a track-latch comparator(which doesn't need above complexity) but my question is very specific to 2-stage open loop type.

Regards

1. I don't understand ur spec. , how can u get common mode voltage from ur output if ur output are the output from comparator (which should be logic 0 or logic 1, so the common mode voltage is always vcc/2)
2. if ur application is open loop type ( comparator-like) , why do u need feedback ?
by the way , in fully-differential comparator there should exist two reference and two inputs, so why worry about the CMFB
3. as I know, gain*BW is a constant in OPamp, so if ur comparator is made from OTA like, u can not get large value of BW

 

[ezt]

Hi.
I agree with Btrend completely. In designing comparators you shouldn't worry about output CM level. Opamp design is another category. Comparator output is a logic level which is vdd for "1" and 0 for "0".
I suggest the following paper in designing dynamic comparators :
L. Sumanen et al, "A mismatch insensitive CMOS Dynamic Comparator for Pipeline A/D Converters", in Proc. ICECS'00, Dec. 2000.

Regards,
EZT

 

[MLR67]

Hi
Comparators are open loops circuits , so stability is not a issue.
EZT may you post this article please ?