Close to tape-out few cells are failing IR check by 5% above the 10% limit. On what bases these can be waved?

There is no waiving of IR violations because those are not DRC. Foundry does not care about how good/bad your design is as long as it respects the rules. It is up to the designer to decide what IR margins are acceptable.

viona_s said:

If IR drop safe limit for the chip 10%, few cells in one region are showing 15% IR drop means failing by 5%. which reports and criteria need to be checked to wave these violations for tape-out.

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If the design already includes extra margins (guardband of >5%), the violation may not impact functionality.

Dropping (vdd!-vss!) by 15% on top of -5% or -10% timing model spec span for supply is going to eat up timing margin if any was there. Foundry will not tell you how much because you'll just try harder to push it next time.

Now that you know it's routable to a clean netlist match, why not "tell it to use 20% fatter core bussing" or use actual engineering to decide on additional overstrapping from I/O core-rails pad adjacent points to the hot spot?

Oh, you thought you were done.

Welcome to the rest of physical design.

If your tools-set offers vdd "heat map" display (and do not neglect vss rise, likely equally bad) this might guide your hand if your eye and brain see the guilty features (or lack of).

If you had relief on high temp spec limit then your timing models might hold more margin but do you? If you held a tighter or higher input supply min, likewise. But this turns into tech management bickering a whole lot faster with slower resolution than just doing the work.