Clocks from same source, need any constraints ?

Status
Not open for further replies.

imbichie

Full Member level 6
Joined
Jul 30, 2010
Messages
381
Helped
55
Reputation
110
Reaction score
54
Trophy points
1,308
Location
Cochin/ Kerala/ India or Bangalore/ Karnataka/ Ind
sites.google.com
Activity points
3,580
Hi All,

I am using Xilinx Virtex7 FPGA for my design and tool using is xilinx Vivado.
In my design there are signals which are driven by CLKA domain and going to CLKB domain and vice verse.
But CLKB is twice the freq as CLKA and both are coming from same source PLL.
So whether I should give any constraints in this case?
 

Unless otherwise specified, as being asynchronous, all clocks are considered synchronous in Vivado. So timing will be considered between CLKA and CLKB domains.

Regards
 

Hi ads-ee,

Thank you for your reply.

I have grouped the CLKA and CLKB in the same group when I give asynchronous group constraints ("set_clock_group -asynchronous -group {CLKA CLKB} -group {CLKC}").
So my doubt is whether I am missing any other constraints between CLKA and CLKB domains.
 

Shouldn't be any other constraints required between CLKA and CLKB if you specified the PLL input clock constraint correctly. Vivado should create generated clocks for the output of the PLL. My advice check the timing reports for unconstrained paths.
 

Status
Not open for further replies.

Similar threads

Menu
Log in
Register
Cookies are required to use this site. You must accept them to continue using the site. Learn more…