Clocking in a capacitor DAC

[majestic.eda]

I am designing an 8-bit capacitor DAC (thermometer coded).

I am confused about the clocking in the DAC. I have gone through several datasheets and I didn't find the CLK pin on any DAC chip!! They just have supply pins, input-pins, output, and Vref. Then what about CLK signal? Are the clocks generated internally or how else?

One more issue: Say my DAC has to operate at 50 MSPS. So does that mean it can process input samples strictly at this rate? Or is this the upper limit?

 

[digi001]

yes.. most DAC and ADC have their own internal clocks. the way most work is with a SOC (start of conversion pin) which you pull low to start a conversion. meanwhile a BUSY signal pin goes high and once the data is ready the BUSY signal goes low. Now the data is ready to be taken off the serial/parallel bus at your convenience (via RD Read pin).

 

[majestic.eda]

@ templemark
Hi.. thanks for replying.
What I understood from ur reply is that SOC (start of conversion) pin is used to provide 'sort of' clock pulses to the DAC (and these pulses initiate the data conversion).

Right now, various blocks in my DAC design work w.r.t a clock signal. At the top-level, this CLK signal has to come from outside world (from the component supplying the digital data samples). I assume that at top level, this same CLK signal will be called SOC (calling it clock may not be appropriate coz this signal may or may not toggle at regular intervals).

Plz correct me if i'm wrong...

 

[digi001]

Well Im not sure about your design, but the Clock signal on most ADC and DAC is internal to the IC. This does not come from the outside world. What happens usually in a DAC is that the digital data is put onto the digital bus first. Then once this happens a pin LDAC is triggered to load the contents of the digital number onto the analog output.

So although it does not share the same clock on as the IC controlling the DAC, they are still syncronous in a way via the LDAC pin.