Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

clocked_lssd

Status
Not open for further replies.

nambulasurya

Newbie level 1
Joined
Aug 13, 2014
Messages
0
Helped
0
Reputation
0
Reaction score
0
Trophy points
0
Activity points
0
Hi everyone,
I am new to DFT,I am facing problem on clocked_ lssd scan insertion tcl script

this is my tcl script

set_attribute lib_search_path ../../lib
set_attribute hdl_search_path ../outputs
set_attribute map_to_master_slave_lssd true /

set_attribute library "slow.lib"


read_hdl "netlist.v"

elaborate
###which technology is using for scan insertion
set_attribute dft_scan_style clocked_lssd_scan
##tells about muxed _scan style variables
define_dft scan_clock_a -create_port mclk
define_dft scan_clock_b -create_port sclk

###It is specifying corresponding master clock port to be connected to MS flipflop during synthesis

set_attribute lssd_master_clock mclk sclk


####specifying testmode
define_dft test_mode -create_port -name Test -active high test
define_dft test_mode -name TM -active high tm


check_dft_rules

set_attribute unmap_scan_flops true

####fix the violations
fix_dft_violations -violations vid_0_async -test_control Test
report dft_registers

set_scan_equivalent -non_scan_cell DFFHQX1 -scan_cell SDFFHQX1
set_scan_equivalent -non_scan_cell DFFSX1 -scan_cell SDFFSX1

replace_scan



define_dft scan_chain -name chain1 -create_port -sdi SI -sdo SO

connect_scan_chains -chains chain1


ERROR:


Scan mapping status report
==========================
Scan mapping: converting flip-flops that pass TDRC.
Scan mapping done: 5 flip-flops mapped to scan.
5 flip-flops mapped to scan using explicit scan equivalent rules.
Category Number Percentage
-----------------------------------------------------------
Scan flip-flops mapped for DFT 5 100.00%
Flip-flops not mapped for DFT
flip-flops not scan replaceable 0 0.00%
flip-flops not targeted for DFT 0 0.00%
-----------------------------------------------------------
Totals 5 100.00%

Starting DFT Scan Configuration for module 'top' in 'normal' mode, with physical flow OFF
Warning : Non-scan flop conversion to scan is done using the replace_scan command. The following register will not be included on a chain. [DFT-512]
: out_reg[3]
Warning : Non-scan flop conversion to scan is done using the replace_scan command. The following register will not be included on a chain. [DFT-512]
: out_reg[2]
Warning : Non-scan flop conversion to scan is done using the replace_scan command. The following register will not be included on a chain. [DFT-512]
: out_reg[0]
Warning : Non-scan flop conversion to scan is done using the replace_scan command. The following register will not be included on a chain. [DFT-512]
: out_reg[1]
Warning : Non-scan flop conversion to scan is done using the replace_scan command. The following register will not be included on a chain. [DFT-512]
: Iset_reg
Warning : Could not connect scan chains. [DFT-415]
: No registers are available to connect into scan chains.
: Check if the status of the flops indicates they failed the DFT rule checker or were marked dont scan. If the flops passed the DFT rule checker, check if they are part of a preserved module. Also check to see if all the elements have been assigned to a configuration mode in which case rerun the command using the -dft_configuration_mode option. Lastly, check if the flops were already connected.
Mapping DFT logic introduced by scan chain connection...


can any one help
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top