Clock Uncertancy vs Clock Freq increase

Hi All,

As for the Synthesis/STA is the same to define the clock uncertainty or just increase clock freq definition in the same number?

Why defining the clock uncertainty is better (I guess it's better)?

Thank you!

In ideal mode the clock signal can arrive at all clock pins simultaneously. But in fact, that perfection is not achievable. So, to anticipate the fact that the clock will arrive at different times at different clock pins, the "ideal mode" clock assumes a clock uncertainty.
Major reasons for the clock does not always arrive exactly one clock period later is :
(a) The insertion delay to the launching flip-flop's clock pin is different than the insertion delay to the capturing flip-flop's clock pin (one paths through the clock tree can be longer than another path). This is called clock skew.
(b) The clock period is not constant. Some clock cycles are longer or shorter than others in a random fashion. This is called clock jitter.
(c) Even if the launching clock path and the capturing clock path are absolutely identical, their path delays can still be different because of on-chip variation. This is where the chip's delay properties vary across the die due to process variations or temperature variations or other reasons. This essentially increases the clock skew.

In clock frequency definition, we give the targetted clock frequency. Uncertainity occurs due to jitter, ocv etc. Can you target a clock frequency for a range of value?

Better increase uncertainty. Because, increasing clock frequency will not issue any new hold violations (hold is freq. independent). But uncertainty will affect both: setup and hold.

oratie said:

Better increase uncertainty. Because, increasing clock frequency will not issue any new hold violations (hold is freq. independent). But uncertainty will affect both: setup and hold.

Click to expand...

that's right.
frequency change wont affect hold but it affect setup.

clock uncertainty is impacted by many more factors than just frequency. it is dependent on the PLL design, choice of Vt's, clock tree to the design etc. all this has to be taken into account during analysis.

clock uncertainty should be independently analyzed rather than mixing with clock frequency.