Would anyone be able to point me in the right direction for where or how i would generate/get the timing constraints file (.const) so I can generate the clock tree? I was thinking that synpl1fy AS1C would generate it for me.. but isn't looking that way.
Please check your skew/uncertainty from RTL to gate level synthesis script(s). You might need to find out the delay by yourself. However, the best way to solve your problem is.... checking with your front-end designers... :roll: