clock tree synthesis for clock gating

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quiet83

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I use clock gating in my design, but it seems the clock tree synthesis only balances the clock to the clock gating cell but not to the leaf register.

I have checked the post-layout simulation results. The clock signals to the gating cell are well aligned. But the gated clock signals to the leaf register are not well aligned.

Is there any solutions to let the tool balance the clock tree passing through the clock gating cell?

Thanks.
 

I don't know which kind of gating you used, but with a latch and AND gate, the clock tree synthesis go through the AND gate and all leaf elements are well balanced.
 

I just use the clock gating cell in the library, and it's latch and "and" gate.
I have checked the results again. The clock signals to the gating latches are well balanced.
But after that, they are not balanced.
Do I add some extra options to let the tool do that?
Thanks.
 

Please make sure in your tool settings that icg is considered as clock cell rather leaf cell.
 

I think the problem is the clock gating cell design itself. The idea of clock gating cell sizing is that it has to match the p/n ratio and rise/fall times of the final and gate as the same as the clock buffers( I am assuming you are using clock buffers). from this there can be a few things
a) clock gating cell VT might be different from the clock buffers Vt.
b) Please check the transition times (rise/fall) for the clock output are same as clock buffer. The transition time specs have to be the same for clock_out of clock gating cell as well as clock buffer.
 

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