Clock Synthesis with Synopsys DC

[giggs11]

synopsys clock buffering

Hi,

I believe clock synthesis measures the clock delay to all clock inputs. With the results, one could opt for buffering to improve clock signal delay to certain clock input of submodules....Is this correct..?

Does any body know how to go about performing these tasks in the order of:

(a) Analysis of clock delays at each clock input in the design

(b) Buffering to improve the delays

The tool of interest is the Synopsys DC and commands to perform these tasks would be most helpful.

Thanks.

 

[eternal_nan]

Hi Giggs,

The tasks that you describe are not done in design compiler, instead they are done during layout in a step called cloclk tree insertion (or synthesis, as you said). The clock tree paramaters are analyised using a static timing analysis tool (like primetime) using the post layout netlist and extracted parasitics.

 

[wadaye]

Hi giggs11:

You shouldn't do CTS in DC.

You should do it after Place.

You can do CTS in SE , ASTRO, or CLOCKWISE in SOC ENCOUNTER.

wang1

 

[giggs11]

Hi,

EternalMan mentioned that Clock Tree Insertion is done after the STA tool reads and analyses the post-layout netlist....and this would be called Clock Synthesis?

Okay, so what you're saying is that STA would identify and instruct the layout tool to place buffers at clock branches to clock inputs...?

Thanks.

 

[linuxluo]

hi,
you can use physical compiler to do what you want about CTS.
pls look up the clock tree generation manual in sold

 

[crek hardman]

Hi,
The normal flow for : DC-> netlist
Astro/Apollo: floorpaln -> placement -> CTS -> route, so CTS will be done after placement, and you also can do it in PC with a CTS license.



Hope this can help you!

 

[gerade]

clock is heavily placement related. that is why usually, we will not do CTS in DC and define all the clock as ideal network

 

[sandusty]

You can have the buffer insertion in the DC to take care of the clock tree. However, the results are not as good as CTS/clock-gen in the back end. Since in the sub-micron/deep-sub-micron the wire load dominated the delay. The wire load could only be estimated after the placement.

If you just need a quick and dirty answer about the delay from clk source to the flops, please take log on your flop number and times the clock buffer delay, than times a constant (which depends on you tech and die size for wire delay).

Good luck,