clock speed for different memory bit width

[cashen224]

Dear Experts,

I have a doubt about the max achievable clock frequency for different bit width of BRAM.

For example I am using the Xilinx kintex7 device and would like to generate a memory with data widths of 1024 bits (one line contains 1024 bits). I have two options:


1. Instantiate a BRAM with data width = 1024 bits, and

2. Instantiate 16 BRAM with data width = 64 bits. While read/write, I split/concatenate the input/out data bus.

My question is which design (1 or 2) would achieve higher clock frequency, or they are basically the same.

thanks for any advise.

 

[tyy38]

At least, 16 Bram will be a big load for CLK signal. Synchronization of CLK will be a risk. Additional CLK driver is needed.

 

[rberek]

The 7 series FPGAs use BRAMs that have a maximum width of 64bits (72 if you use parity). Therefore whether or not you use Coregen to generate a x1024 memory, or you infer one in your code, or you generate 16 x64 memories, you will physically end up with 16 memories. Moreover, since each BRAM is a maximum of 32 kbits (36k if you use parity), all your BRAMs would be 512 bits deep. So if you need a x1024 deeper than that, you would need 32 or more BRAMs.

Having said all that, Coregen would take care of the timing issues for you when it generates the memory.

r.b.

r.b.