external clock termination
PCB TRACE GENERAL GUIDELINES
• To maximize signal integrity, the use of controlled impedance traces of Z0
= 50 ohms (±10%) characteristic impedance should be considered.
• Consider routing high frequency signals on layers adjacent to a common
reference plane (i.e. power or ground).
• Route each data group (DQS and DQ) on the same layer to match
propagation delays and minimize skew.
• Route similar signals (i.e. address bus or data bus) on the same layer to
match propagation delays and minimize signal –signal skew.
• Separate low frequency and high frequency signals to minimize crosstalk.
• Traces should be routed in a daisy chain manner versus a star topology
to maintain signal integrity and facilitate a termination connection (if
required).
Averything above is true, but this guideline describes situation with data throughput rates of >5-10Gbps.
Below is another example of clock termination on a PCB .. but again, it was implemented in >1GHz system ..
I dont want to use any particular cut-off frequency above which you will use 50Ω terminations .. let common sense prevail ..
So, 20MHz, 50MHz, .. 100MHz if you really want to, you can place two 1kΩ resistors, one between signal and 0V, and one between signal and +5V, but I don't think it is necessary ..